a. The trigger input of “Decode Inhibit” one-shot U56-10 to
inhibit the decoder for .25 seconds and prevent transmitter
turn-on during that time.
b. “Inhibit K2” gate U52-11 to de-energize the PA Power
Supply contactors.
P.6.7
Power Level Latch Outputs
The LOW, MEDIUM, and HIGH power mode commands from
U40 go through the AND gates in U39 to:
a. Power control up-down counter gates.
b. Indicator circuits.
c. The “Turn-On” request gate.
P.6.8
Inhibit Gates U39-3, U39-6 AND U39-8
The output of each AND gate is logic HIGH only if both inputs
are HIGH. One input to each gate is the LOW, MEDIUM or
HIGH power level logic signal from U40. The second input is
from the “INHIBIT K2” line from U52-8. If this line is HIGH,
the output of U40 appears at the gate output. If the inhibit line
is LOW, the AND gate outputs are forced LOW and any output
from U40 is inhibited from going to any other circuits.
P.6.9
Turn-on Request Gate (U52) and Inverter (U55)
A “TURN ON REQUEST-H” signal is generated each time
a new power level command is latched unless the “INHIBIT
K2” signal from the turn-on/turn-off logic blocks the latch
outputs. The three ”power level” logic outputs from U40 are
fed to U52-1, 2, and 13. When a power level is selected, one
of the three inputs goes HIGH and U52-12 goes LOW. The
signal is inverted at U55-12 to generate the “TURN ON
REQUEST-H” signal. The LOW to HIGH transition triggers
U56 in the turn-on/turn-off control section. The following
events then happen simultaneously:
1. The Step-start sequence begins
2. The Oscillator output is switched ON
3. The DC Regulator circuits are enabled
4. The Driver Encoder/Temp Sense Board turns the
Driver Modules ON
P.6.10
Up-Down Counters: Setting and Storing
Digital Power Data
This section includes Up-down Counters, Counter Control
Gates, and Inhibit Circuits. Each power level circuit includes a
set of up-down counters, counter control gates, and inhibit
circuits. This section generates and stores three 12-bit BCD
(Binary Coded Decimal) power output control signals.
P.6.10.1
Up-Down Counters U6-U8, U18-U20, and U30-U32
Refer to Sheet 3 of the Controller Schematic Diagram for the
following discussion.
Each counter has a four bit BCD output, and counts from “0” to
”9”. The counter “counts” when a low-to-high transition occurs
at the “count up” or “count down” input (pins 5 and 4). There
are three sets of Up-Down Counters, one set for each power
mode, as follows:
a. HIGH: U8 (1’s), U7 (10’s), U6 (100’s).
b. MEDIUM: U20 (1’s), U19 (10’s), U18 (100’s).
c. LOW: U32 (1’s), U31 (10’s) and U30 (100’s).
The output of each set of counters is a 3-digit BCD (Binary
Coded Decimal) digital power control signal. To raise or lower
power, a series of clock pulses is applied to either the UP or
DOWN input of the “ones” digit counter.
P.6.10.2
“Carry”
When counting UP, each counter goes to “9,” then goes back to
“0” and begins counting up again. When the counter goes from
“9” to “0,” a “carry” output is generated; the “carry” goes to the
Figure P-2. Power Control Logic: Simplified Diagram
817 2099 025
Section P - Controller (A38)
Rev. S: 05-02-97
888-2297-002
P-9
WARNING: Disconnect primary power prior to servicing.
