GE Multilin L60, Instruction Manual

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GE Multilin L60 Line Phase Comparison System 8-21
8 THEORY OF OPERATION 8.1 OVERVIEW
8
The receiver output is now symmetrical, but may be phase shifted in the lagging direction from the actual keying signal at
the remote terminal. This latter result is not desirable, but fortunately it may be mitigated. In addition to this there is the
propagation delay in getting the communication signal from the remote transmitter to the local receiver (1 millisecond per
186 miles) plus the delay in the receiver itself. All of these add to each other to produce a receiver output that may be sig-
nificantly phase delayed from the current at the remote end of the line.
This is undesirable because it introduces an error in the phase comparison. There is no way to eliminate this phase delay
but there is a way to compensate for it. This compensation is accomplished by the phase delay timer in the comparer input
circuit.
b) PHASE DELAY ADJUSTMENT
The phase delay adjustment is a timer that is set with a pickup and a dropout delay that are equal to each other so that it
introduces a phase delay without affecting the symmetry of the input signal. Its output is the same shape as that of the
squaring amplifier but delayed in time by the setting. This time delay setting is made in the field to be just equal to the sum
of the three delays (symmetry adjustment, propagation, and receiver) discussed above. Thus, with this arrangement in the
scheme of Figure 8-15, an external fault would produce a output from the symmetry adjustment logic exactly in phase and
symmetrical with the output of the phase delay logic. This is necessary for proper blocking. For internal faults the output
from the phase delay timer would be symmetrical with, but 180 degrees out of phase with the receiver output. This is nec-
essary for tripping. It should be recognized that any errors in these adjustments can reduce the tripping margins for internal
faults and/or reduce the blocking margins during external faults.
It is interesting to note that the setting of the phase delay timer is dependent on the channel operating time, and that the
total tripping time of the scheme is affected by this timer setting. Thus, the tripping speed of the scheme is to that degree
dependent on the channel operating time.
c) TRANSIENT BLOCKING
Transient blocking is a feature that is included in all phase comparison schemes. It adds to the security of the scheme dur-
ing and immediately after the clearing of external faults. Figure 8-16 is a representation of Figure 8-15 except with the tran-
sient blocking logic added. This consists of AND3, AND4 and the (15-99)/(15-99) transient blocking timer.
Figure 8–16: BLOCKING SCHEME WITH TRANSIENT BLOCKING LOGIC