C141-E171-03EN
IN-1
Index
A
active idle mode 6-7
active mode 6-7
alternate cylinder assignment processing
6-10
alternating processing,
automatic 6-11
for defective sector 6-10
for defective sector 6-10
area, spare 6-9
assignment processing, alternate cylinder
6-10
automatic alternating processing 6-11
B
blower 4-3
C
caching operation 6-12, 6-20
command, non-sequential 6-16
command, sequential 6-16
command, target of caching 6-13
command that is target of caching 6-13,
6-20
D
data, target of caching 6-13
data buffer structure 6-12
data that is target of caching 6-13
data transfer,
multiword 5-128
PIO 5-127
Ultra DMA 5-129
defect processing 6-9
device pausing Ultra DMA data out burst
5-139
device response 6-2
to reset 6-2
device terminating Ultra DMA data
in burst 5-135, 5-141
out burst 5-141
E
enabling and disabling 6-21
F
fluctuation,current 1-7
full hit 6-18
H
hit, full 6-18
hit, no 6-15
hit, partial 6-19
hit, sequential 6-17
host pausing Ultra DMA data in burst
5-134
host terminating Ultra DMA data
in burst 5-136
out burst 5-140
I
initiaitng, Ultra DMA data
in burst 5-129
out burst 5-137
initiating Ultra DMA data
in burst 5-129
out burst 5-137
invalidating, caching-target data 6-13
invalidating caching-target data 6-13
invalidation of cached data 6-20
L
low power idle mode 6-7
M
mean time, mean time between failures
miss, hit 6-15
miss-hit 6-15
mode, active 6-7
mode, active idle 6-7
mode, power save 6-7
mode, sleep 6-8
mode, standby 6-8
multiword data transfer 5-128
multiword DMA data transfer timing 5-128
N
no hit 6-14
non-sequential command 6-16
Summary of Contents for MHS2020AT
Page 1: ...C141 E171 03EN MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES PRODUCT MANUAL ...
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Page 60: ...Theory of Device Operation 4 6 C141 E171 03EN Figure 4 3 Circuit Configuration ...
Page 190: ...Interface 5 114 C141 E171 03EN g d f f d e Figure 5 7 Normal DMA data transfer ...
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