Interface
5-106
C141-E171-03EN
5.4 Command Protocol
The host should confirm that the BSY bit of the Status register of the device is 0
prior to issue a command. If BSY bit is 1, the host should wait for issuing a
command until BSY bit is cleared to 0.
Commands can be executed only when the DRDY bit of the Status register is 1.
However, the following commands can be executed even if DRDY bit is 0.
•
EXECUTE DEVICE DIAGNOSTIC
•
INITIALIZE DEVICE PARAMETERS
5.4.1 PIO Data transferring commands from device to host
The execution of the following commands involves data transfer from the device
to the host.
•
IDENTIFY DEVICE.
•
READ SECTOR(S) (EXT)
•
READ LONG
•
READ BUFFER
•
SMART READ DATA
•
SMART READ LOG SECTOR
The execution of these commands includes the transfer one or more sectors of
data from the device to the host. In the READ LONG command, 516 bytes are
transferred. Following shows the protocol outline.
a)
The host writes any required parameters to the Features, Sector Count, Sector
Number, Cylinder, and Device/Head registers.
b)
The host writes a command code to the Command register.
c)
The device sets the BSY bit of the Status register and prepares for data
transfer.
d)
When one sector of data is available for transfer to the host, the device sets
DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.
e)
After detecting the INTRQ signal assertion, the host reads the Status register.
The host reads one sector of data via the Data register. In response to the
Status register being read, the device negates the INTRQ signal.
f)
The drive clears DRQ bit to 0. If transfer of another sector is requested, the
device sets the BSY bit and steps d) and after are repeated.
Even if an error is encountered, the device prepares for data transfer by setting the
DRQ bit. Whether or not to transfer the data is determined for each host. In other
Summary of Contents for MHS2020AT
Page 1: ...C141 E171 03EN MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES PRODUCT MANUAL ...
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Page 60: ...Theory of Device Operation 4 6 C141 E171 03EN Figure 4 3 Circuit Configuration ...
Page 190: ...Interface 5 114 C141 E171 03EN g d f f d e Figure 5 7 Normal DMA data transfer ...
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