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5.5 Ultra DMA Feature Set

C141-E171-03EN

5-125

13) The host shall neither negate STOP nor HSTROBE until at least t

ACK

after

negating DMACK-.

14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until

at least t

ACK

after negating DMACK.

5.5.5 Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error
has occurred during an Ultra DMA burst, and reporting any error that occurs at
the end of a command.

a)

Both the host and the device shall have a 16-bit CRC calculation function.

b)

Both the host and the device shall calculate a CRC value for each Ultra DMA
burst.

c)

The CRC function in the host and the device shall be initialized with a seed
of 4ABAh at the beginning of an Ultra DMA burst before any data is
transferred.

d)

For each STROBE transition used for data transfer, both the host and the
device shall calculate a new CRC value by applying the CRC polynomial to
the current value of their individual CRC functions and the word being
transferred. CRC is not calculated for the return of STROBE to the asserted
state after the Ultra DMA burst termination request has been acknowledged.

e)

At the end of any Ultra DMA burst the host shall send the results of its CRC
calculation function to the device on DD (15:0) with the negation of
DMACK-.

f)

The device shall then compare the CRC data from the host with the
calculated value in its own CRC calculation function. If the two values do
not match, the device shall save the error and report it at the end of the
command. A subsequent Ultra DMA burst for the same command that does
not have a CRC error shall not clear an error saved from a previous Ultra
DMa burst in the same command. If a miscompare error occurs during one
or more Ultra DMA bursts for any one command, at the end of the command,
the device shall report the first error that occurred.

g)

For READ DMA or WRITE DMA commands: When a CRC error is
detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2
in the Error register) to one. ICRC is defined as the "Interface CRC Error"
bit. The host shall respond to this error by re-issuing the command.

h)

A host may send extra data words on the last Ultra DMA burst of a data out
command. If a device determines that all data has been transferred for a
command, the device shall terminate the burst. A device may have already
received more data words than were required for the command. These extra
words are used by both the host and the device to calculate the CRC, but, on
an Ultra DMA data out burst, the extra words shall be discarded by the
device.

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Summary of Contents for MHS2020AT

Page 1: ...C141 E171 03EN MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...1 03EN Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2002 07 12 02 2002 07 31 03 2002 09 20 1 Section s with asterisk refer to the previous edition when those were deleted ...

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Page 5: ... an overview of the MHS Series and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the MHS Series and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the MHS Series CHAPTER 4 Theory of Device Operation T...

Page 6: ...y In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main...

Page 7: ...t at the back of this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system o...

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Page 9: ...rform the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handl...

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Page 11: ...ES PRODUCT MANUAL C141 E171 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES MAINTENANCE MANUAL C141 F059 Maintenance and Diagnosis Removal and Replacement Procedure ...

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Page 13: ...number 1 5 1 3 Power Requirements 1 5 1 4 Environmental Specifications 1 8 1 5 Acoustic Noise 1 9 1 6 Shock and Vibration 1 9 1 7 Reliability 1 10 1 8 Error Rate 1 11 1 9 Media Defects 1 11 1 10 Load Unload Function 1 11 1 11 Advanced Power Management 1 12 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2...

Page 14: ... default setting 3 12 3 4 3 Master drive slave drive setting 3 12 3 4 4 CSEL setting 3 13 3 4 5 Power Up in Standby setting 3 14 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Head 4 2 4 2 3 Spindle 4 3 4 2 4 Actuator 4 3 4 2 5 Air filter 4 3 4 3 Circuit Configuration 4 4 4 4 Power on Sequence 4 7 4 5 Self calibration 4 8 4 5 1 Self calibration ...

Page 15: ...Signal assignment on the connector 5 3 5 2 Logical Interface 5 6 5 2 1 I O registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 14 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 18 5 3 3 Error posting 5 104 5 4 Command Protocol 5 106 5 4 1 PIO Data transferring commands from device to host 5 106 5 4 2 PIO Data transferring comm...

Page 16: ...er 5 128 5 6 3 Ultra DMA data transfer 5 129 5 6 3 1 Initiating an Ultra DMA data in burst 5 129 5 6 3 2 Ultra DMA data burst timing requirements 5 130 5 6 3 3 Sustained Ultra DMA data in burst 5 133 5 6 3 4 Host pausing an Ultra DMA data in burst 5 134 5 6 3 5 Device terminating an Ultra DMA data in burst 5 135 5 6 3 6 Host terminating an Ultra DMA data in burst 5 136 5 6 3 7 Initiating an Ultra ...

Page 17: ... Alternating processing for defective sectors 6 10 6 4 Read ahead Cache 6 12 6 4 1 Data buffer structure 6 12 6 4 2 Caching operation 6 12 6 4 3 Using the read segment buffer 6 15 6 4 3 1 Miss hit no hit 6 15 6 4 3 2 Sequential reading 6 16 6 4 3 3 Full hit 6 18 6 4 3 4 Partial hit 6 19 6 5 Write Cache 6 20 6 5 1 Caching operation 6 20 Glossary GL 1 Acronyms and Abbreviations AB 1 Index IN 1 ...

Page 18: ...3 8 Figure 3 8 Connector locations 3 9 Figure 3 9 Cable connections 3 10 Figure 3 10 Power supply connector pins CN1 3 11 Figure 3 11 Jumper location 3 11 Figure 3 12 Factory default setting 3 12 Figure 3 13 Jumper setting of master or slave drive 3 12 Figure 3 14 CSEL setting 3 13 Figure 3 15 Example 1 of Cable Select 3 13 Figure 3 16 Example 2 of Cable Select 3 14 Figure 4 1 Head structure 4 3 F...

Page 19: ...ined Ultra DMA data in burst 5 133 Figure 5 13 Host pausing an Ultra DMA data in burst 5 134 Figure 5 14 Device terminating an Ultra DMA data in burst 5 135 Figure 5 15 Host terminating an Ultra DMA data in burst 5 136 Figure 5 16 Initiating an Ultra DMA data out burst 5 137 Figure 5 17 Sustained Ultra DMA data out burst 5 138 Figure 5 18 Device pausing an Ultra DMA data out burst 5 139 Figure 5 1...

Page 20: ...e 5 6 Diagnostic code 5 56 Table 5 7 Features Register values subcommands and functions 5 68 Table 5 8 Format of device attribute value data 5 72 Table 5 9 Format of insurance failure threshold value data 5 72 Table 5 10 Log Directory Data Format 5 77 Table 5 11 Data format of SMART Summary Error Log 5 78 Table 5 11 1 Data format of SMART Comprehensive Error Log 5 79 Table 5 12 SMART self test log...

Page 21: ...on 1 7 Reliability 1 8 Error Rate 1 9 Media Defects 1 10 Load Unload Function 1 11 Advanced Power Management Overview and features are described in this chapter and specifications and power requirement are described The MHS Series are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable ...

Page 22: ...ports an external data rate up to 100 MB s U DMA mode 5 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode The power save mode feature for idle operation stand by and sleep modes makes The disk drives the MHS Series ideal for applicat...

Page 23: ...e read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives the MHS Series can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk drives the MHS Series themselves att...

Page 24: ...rack Density 3 14 K track mm 79 800 TPI Bit Density 26 26 K bit mm 667 KBPI 23 62 K bit mm 600 KBPI 26 26 K bit mm 667 KBPI 21 65 K bit mm 550 KBPI Rotational Speed 4 200 rpm 1 Average Latency 7 14 ms Positioning time read and seek Minimum Track to Track Average Maximum Full 1 5 ms typ Read 12 ms typ 22 ms typ Start time Typ 3 5 sec Interface ATA 6 Max Cable length 0 46 m equipped with expansion f...

Page 25: ...83 16 63 MHS2030AT 8 45 GB 16 383 16 63 MHS2020AT 8 45 GB 16 383 16 63 1 On using for the units of BIOS parameter 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the MHS Series Table 1 2 Model names and product numbers Model Name Capacity user area Mounting screw Order No MHS2060AT 60 GB M3 depth 3 CA06272 B042 MHS2040AT 40 GB M3 depth 3 CA06272 B83100DX MHS20...

Page 26: ...oltage like the bottom figure isn t to occur at 5V when power is turned off and a thing with no ringing Permissible level 0 2V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 1 Negative voltage at 5V when power is turned off ...

Page 27: ...S2060AT 0 011 W GB rank E MHS2040AT 0 022 W GB rank D MHS2030AT 0 022 W GB rank D MHS2020AT 1 Current at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect nominal values for 5V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the v...

Page 28: ...ed with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non...

Page 29: ...e 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 2207 m s2 0 peak 225G 0 peak 2ms duration without non recovere...

Page 30: ...o repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occ...

Page 31: ...tioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 10 7 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk the MHS Series are formatted prior to shipment from the factory low level format Thus the hosts see a defect free devices Alternate sectors are automatically accessed by the disk drive The u...

Page 32: ...is device recommends as follows 1 Disk Flush Flush Cache command execution 2 Head Unload Standby Immediate command execution 3 Wait Status Please wait to complete the command by Status Register 4 HDD power supply cutting 1 11Advanced Power Management The disk drive shifts to the three kinds of APM modes automatically under the Idle condition The APM mode can be chosen with a Sector Count register ...

Page 33: ...ck Low Power Idle VCM Unload Standby Spin Off Mode 0 3sec N A N A Mode 1 3sec 10sec N A Mode 2 3sec 4sec 60sec Mode 0 It shifts to Active Idle in 3 seconds from the Idle condition Mode 1 It shifts to Low power Idle in 13 seconds from the Idle condition Mode 2 It shifts to Standby in 67 seconds from the Idle condition The set point is reflected on WORD91 of the IDENTITY DEVICE command APM mode is r...

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Page 35: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 36: ...sk is 65 mm The inner diameter is 20 mm The number of disks used varies with the model as described below MHS2060AT 2 disks MHS2040AT 2 disks MHS2030AT 1 disk MHS2020AT 1 disk 2 Head The heads are of the load unload L UL type The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts Figure 2 2 illustrates the configuration of the disks and heads of ...

Page 37: ...ot on or if the spindle motor is stopped the head assembly stays on the ramp out of the disk and is fixed by a mechanical lock 5 Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the ci...

Page 38: ...DMA mode 5 100 MB s 2 2 2 1 drive connection MHC2032AT MHC2040AT Figure 2 3 1 drive system configuration 2 2 3 2 drives connection MHC2032AT MHC2040AT MHC2032AT MHC2040AT Host adaptor Note When the drive that is not conformed to ATA is connected to the disk drive above configuration the operation is not guaranteed Figure 2 4 2 drives configuration MHG2102AT MHH2064AT MHH2032AT MHS2060AT MHS2040AT ...

Page 39: ...lk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 6 standard and the cable length between the HA and the disk drive should be as short as possible No need to push the top cover of the disk drive If the over powe...

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Page 41: ...er Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives For information about handling this hard disk drive and the system installation procedure refer to the following Integration Guide C141 E144 ...

Page 42: ...Installation Conditions 3 2 C141 E171 03EN 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm Figure 3 1 Dimensions ...

Page 43: ...ee the FUJITSU 2 5 INCH HDD INTEGRATION GUIDANCE C141 E144 01EN 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive a Horizontal 1 b Horizontal 1 c Vertical 1 d Vertical 2 e Vertical 3 f Vertical 4 Figure 3 2 Orientation gravity gravity gravity ...

Page 44: ...5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Figure 3 3 Mounting frame structure Screw Screw Details of B Details of A 3 0 or less 3 0 or less Frame of system cabinet Fr...

Page 45: ...ecause of breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 For breather hole of Figure 3 4 at least do not allow its around φ2 4 to block Figure 3 4 Location of breather ...

Page 46: ...ace temperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperat...

Page 47: ...not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following cautions and handle th...

Page 48: ...orque of the screw strictly M3 0 49N m 5kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to avoid fa...

Page 49: ... Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals Figure 3 8 Connector locations Connector setting pins PCA ...

Page 50: ... 89361 144 FCI IMPORTANT For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 9 shows how to connect the devices Host system DC Power supply ...

Page 51: ... 3 10 shows the pin assignment of the power supply connector CN1 Figure 3 10 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 11 shows the location of the jumpers to select drive configuration and functions Figure 3 11 Jumper location ...

Page 52: ...n at the factory Figure 3 12 Factory default setting 3 4 3 Master drive slave drive setting Master drive disk drive 0 or slave drive disk drive 1 is selected b Slave drive a Master drive Open Open Short Open A 1 C B D 2 B D 2 A C 1 Figure 3 13 Jumper setting of master or slave drive Note Pins A and C should be open Open ...

Page 53: ...ion using unique interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive is identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is i...

Page 54: ...Installation Conditions 3 14 C141 E171 03EN Figure 3 16 Example 2 of Cable Select 3 4 5 Power Up in Standby setting When pin C is grounded the drive does not spin up at power on drive drive ...

Page 55: ...4 3 Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 56: ...dle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 4 2 1 Disk The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm The MHS2060AT and MHS2040AT have two disks and MHS2030AT and MHS2020AT have one disk Servo data is recor...

Page 57: ... The VCM moves the head carriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of t...

Page 58: ... circuits 48 50 RLL Limited encoder Run Length and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor ...

Page 59: ...4 3 Circuit Configuration C141 E171 03EN 4 5 5 0V 3 3V 3 0V S DRAM SVC HDIC F ROM MCU HDC RDC 2 0V 1 8 V generator circuit Figure 4 2 Power Supply Configuration ...

Page 60: ...Theory of Device Operation 4 6 C141 E171 03EN Figure 4 3 Circuit Configuration ...

Page 61: ...he spindle motor b The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The disk drive sets up a requirement for execution of self seek calibration ...

Page 62: ...and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system Start Self diagnosis 1 MPU bus test Internal reg...

Page 63: ...rmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole...

Page 64: ...e read write circuit consists of the read write preamplifier HDIC the write circuit the read circuit and the time base generator in the read channel RDC Figure 4 4 is a block diagram of the read write circuit 4 6 1 Read write preamplifier HDIC HDIC equips a read preamplifier and a write current switch that sets the bias current to the MR device and the current in writing Each channel is connected ...

Page 65: ...diagram HDIC WDX WDY RDX RDY Write PreCompen sation Serial I O Registers Digital PLL Flash Digitizer MEEPR Viterbi Detect 16 17 ENDEC ServoPulse Detector Programmable Filter AGC Amplifier RDC SD SC SE Position A B C D to reg WTGATE REFCLK RDGATE DATA 7 0 RWCLK SRV_OUT 1 0 SRV_CLK ...

Page 66: ...he AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut o...

Page 67: ...the survivor path sequence 6 ENDEC This circuit converts the 50 bit read data into the 48 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and t...

Page 68: ... control circuit Figure 4 7 is the block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 7 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU uses DSP and executes startup of the spindle motor movement to the reference cylinder seek to the specified cylinder and calibration operations Main internal operation of the MPU are sho...

Page 69: ...d to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration valu...

Page 70: ...d C D processed 3 D A converter DAC The control program calculates the specified data value digital value of the VCM drive current and the value is converted from digital to analog so that an analog output voltage is sent to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 5 Spindle motor control circuit The spindle ...

Page 71: ... below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving ...

Page 72: ... Code W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase PAD CYLn 1 CYLn CYLn 1 n even number Diameter direction Circumference Direction Erase DC erase area OGB Data area IGB expand Servo frame 140 servo frames per revolution ...

Page 73: ... from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 6 blocks write read recovery servo mark gray code servo A to D and PAD Figure 4 9 shows the servo frame format Figure 4 9 Servo frame format ...

Page 74: ...recorded on the data surface The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to...

Page 75: ...fference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC here...

Page 76: ...nal from the SVC and waits till the rotational speed reaches 4 200 rpm When the rotational speed reaches 4 200 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The SVC calculates a time for one revolution of the spindle motor based on the PHASE signal The MPU takes a difference between the current time and a time for one revolution at 4 200 rpm that the MPU already recognized The...

Page 77: ...PTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings ...

Page 78: ... DMA REQUEST INTRO INTERRUPT REQUEST DIOW I O WRITE STOP STOP DURING ULTRA DMA DATA BURSTS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST 5V DC 5 volt Host IORDY I O READY DDMARDY DMA READY DURING ULTR...

Page 79: ...9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 MSTR PUS KEY RESET DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 MSTR ENCSEL ENCSEL KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND reser...

Page 80: ...ertion of the STOP signal asserted by the host later indicates that the transfer has been suspended DIOR I Read strobe signal from the host to read the device register or data port HDMARDY I Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate...

Page 81: ...nd a slave device is present This signal is pulled up to 5 V through 10 kΩ resistor at each device IORDY O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system DDMARDY O Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device to inform the host tha...

Page 82: ...nal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports ...

Page 83: ...gh X 1F5 L H H H L Device Head Device Head X 1F6 L H H H H Status Command X 1F7 L L X X X Invalid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit da...

Page 84: ...tes the status of the command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at the completion of command execution other than diagnostic command Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC ...

Page 85: ...t is used with SET FEATURES command to enable or disable caching 4 Sector Count register X 1F2 The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 With the EXT system command the sector count is 65536 when value of this register is X 00...

Page 86: ...ss At the end of a command the contents of this register are updated to the current cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 Under the LBA mode of the EXT system command LBA bits 39 to 32 are set in the first setting and LBA bits 15 to 8 are set in the second setting 7 Cylinder High register X 1F5 The contents of this register indicates high order 8 bits of the d...

Page 87: ...ode of the EXT command Bit 1 HS1 CHS mode head address 1 2 1 bit 25 for LBA mode Unused under the LBA mode of the EXT command Bit 0 HS0 CHS mode head address 0 2 0 bit 24 for LBA mode Unused under the LBA mode of the EXT command 9 Status register X 1F7 The contents of this register indicate the status of the device The contents of this register are updated at the completion of each command When th...

Page 88: ...WRITE SECTOR S or WRITE BUFFER command Within 5 µs following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to...

Page 89: ...mediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written 5 2 3 Control block registers 1 Alternate Status register X 3F6 The Alternate Status register contains the same information as the Status register of the command block register The onl...

Page 90: ...e Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Commands The host system issues a command to the device by writing necessary parameters in related...

Page 91: ... 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D SET MAX 1 1 1 1 1 0 0 1 N Y Y Y Y READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N ...

Page 92: ... PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D DEVICE CONFIGURATION 1 0 1 1 0 0 0 1 N N N N D SET MAX ADDRESS 1 1 1 1 1 0 0 1 N Y Y Y Y SET MAX SET PASSWORD 1 1 1 1 1 0 0 1 Y N N N Y SET MAX ...

Page 93: ...0 1 N Y Y Y D READ DMA EXT 0 0 1 0 0 1 0 1 N Y Y Y D WRITE MULTIPLE EXT 0 0 1 1 1 0 0 1 N Y Y Y D READ MULTIPLE EXT 0 0 1 0 1 0 0 1 N Y Y Y D WRITE SECTOR S EXT 0 0 1 1 0 1 0 0 N Y Y Y D READ SECTOR S EXT 0 0 1 0 0 1 0 0 N Y Y Y D Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R Retry at error 1 Without retry 0 With retry ...

Page 94: ...READ SECTOR S At command issuance I O registers setting contents Bit 7 6 5 4 3 2 1 0 1F7H CM 0 0 1 0 0 0 0 0 1F6H DH x L x DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At command completion I O registers contents to be read Bit 7 6 5 4 3 2 1 0 1F7H ST Status information 1F6H...

Page 95: ...r Number registers Number of sectors can be specified from 1 to 256 sectors To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device reads the target sector If an error occurs retry...

Page 96: ...tors of which data was not transferred is set in this register 2 READ MULTIPLE X C4 The READ MULTIPLE Command performs the same as the READ SECTOR S Command except that when the device is ready to transfer data for a block of sectors and enters the interrupt pending state only before the data transfer for the first sector of the block sectors In the READ MULTIPLE command operation the DRQ bit of t...

Page 97: ... an ABORTED COMMAND error Figure 5 2 shows an example of the execution of the READ MULTIPLE command Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1F7H CM 1 1 0 0 0 1 0 0 1F6...

Page 98: ... status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the...

Page 99: ...s not transferred is set in this register 4 READ VERIFY SECTOR S X 40 or X 41 This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain ...

Page 100: ...address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified from 1 to 256 sectors A sector count of 0 requests 256 sectors Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2...

Page 101: ...nts 1F7H CM 0 0 1 1 0 0 0 R 1F6H DH x L x DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder...

Page 102: ...f sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after...

Page 103: ... SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only on...

Page 104: ...rmation 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command excep...

Page 105: ...F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to X F This command performs the calibration Upon receipt of this command the device sets BSY bit of the S...

Page 106: ...L 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information Note Also executable in LBA mode 10 SEEK X 7x x X 0 to X F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt In the LBA mode this command performs the seek operatio...

Page 107: ...X 91 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylinder with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is ...

Page 108: ...C 1F1H ER xx xx xx Number of sectors track Error information 12 IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information from the device Upon receipt of this command the drive sets the BSY bit to one prepares to transfer the 256 words of device identification data to the host sets the DRQ bit to one clears the BSY bit to zero and generates an interrupt ...

Page 109: ...he same way as the Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 1 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 110: ...5 4 Information to be read by IDENTIFY DEVICE command 1 of 3 Word Value Description 0 X 045A General Configuration 1 1 2 Number of Logical cylinders 2 2 X xxxx Detailed Configuration 19 3 2 Number of Logical Heads 2 4 5 X 0000 Undefined 6 2 Number of Logical sectors per Logical track 2 7 9 X 0000 Undefined 10 19 Set by a device Serial number ASCII code 20 characters right 20 X 0003 Undefined 21 X ...

Page 111: ...umber of current sectors 59 6 Transfer sector count currently set by READ WRITE MULTIPLE command 6 60 61 2 Total number of user addressable sectors LBA mode only 2 62 X 0000 Reserved 63 X xx07 Multiword DMA transfer mode 7 64 X 0003 Advance PIO transfer mode support status 8 65 X 0078 Minimum multiword DMA transfer cycle time per word 120 ns 66 X 0078 Manufacturer s recommended DMA transfer cycle ...

Page 112: ...0000 Reserved 100 103 X xx Total number of sectors accessible by users in the 48 bit LBA mode 104 127 X 00 Reserved 128 X 0xxx Security status 18 129 159 X 0000 Undefined 160 254 X 0000 Reserved 255 X xxA5 Check sum The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255 in byte units 1 Word 0 General configuration Bit 15 ATA device 0 ATAPI device ...

Page 113: ...complete C837h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete Others Reserved 3 Word 49 Capabilities Bit 15 14 Reserved Bit 13 Standby timer value Factory default is 0 ATA spec is 1 Bit 12 Reserved Bit 11 1 Supported Bit 10 0 Disable inhibition Bit 7 0 Undefined Bit 8 1 LBA Supported Bit 9 1 DMA Supported 20 W...

Page 114: ...DMA transfer mode Bit 15 11 Reserved Bit 10 1 multiword DMA mode 2 is selected Bit 9 1 multiword DMA mode 1 is selected Bit 8 1 multiword DMA mode 0 is selected Bit 7 3 Reserved Bit 2 1 Multiword DMA mode 2 1 and 0 supported Bit 1 0 1 Bit 1 1 Multiword DMA mode 1 and 0 supported Bit 0 1 Bit 0 1 Mode 0 8 Word 64 Advance PIO transfer mode support status Bit 15 8 Reserved Bit 7 0 Advance PIO transfer...

Page 115: ... 1 Supports the PACKET command feature set Bit 3 1 Supports the power management feature set Bit 2 1 Supports the Removable Media feature set Bit 1 1 Supports the Security Mode feature set Bit 0 1 Supports the SMART feature set 11 WORD 83 Bits 15 14 Undefined Bit 13 1 FLUSH CACHE EXT command supported Bit 12 1 FLUSH CACHE command supported Bit 11 1 Device Configuration Overlay feature set supporte...

Page 116: ...ndefined Bit 14 1 Supports the NOP command Bit 13 1 Supports the READ BUFFER command Bit 12 1 Supports the WRITE BUFFER command Bit 11 Undefined Bit 10 1 Supports the Host Protected Area function Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Enables the SERVICE interrupt From the SET FEATURES command Bit 7 1 Enables the release interrupt From the SET FEATURES command Bit 6 1 Enables the read c...

Page 117: ...atus Notification function Bit 3 1 Enables the Advanced Power Management function Bits 2 0 Same definition as WORD 83 15 WORD 87 Bits 15 0 Bits 14 1 Bits 13 2 Reserved Bit 1 0 Same definition as WORD 84 16 WORD 88 Bit 15 8 Currently used Ultra DMA transfer mode Bit 13 1 Mode 5 is selected Bit 12 1 Mode 4 is selected Bit 11 1 Mode 3 is selected Bit 10 1 Mode 2 is selected Bit 9 1 Mode 1 is selected...

Page 118: ...1 1 Device asserts PDIAG Bit 10 9 Method for deciding the device No of Device 1 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Bit 8 1 In the case of device 1 Bits 7 0 In the case of Device 0 master drive a valid value is set Bit 7 Reserved Bit 6 1 Device 1 is selected Device 0 responds Bit 5 1 Device 0 assertion of DASP was detected Bit 4 1 Device 0 assertion of PDIAG was ...

Page 119: ... host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or...

Page 120: ... power management mode to the default mode X AA Enables the read cache function X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands X C2 Disables the Acoustic management function X CC Enables the reverting to power on default settings after software reset 1 1 Although there is a response to the command nothing is done At power on or after hardware reset the default mode...

Page 121: ...de The host sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND e...

Page 122: ... for a specific time The sequence in which the power management level shifts is from Active Idle to Low Power Idle to Standby The Mode 2 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to their default values when power on or a hardware or software reset occurs for the drive 3 Automatic Acoustic Management AAM The host writes to the...

Page 123: ...s the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIP...

Page 124: ...d WRITE MULTIPLE command operation are disabled as the default mode At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx Sector count block Error information 16 SET MAX F9 SET MAX Features Register Values Value Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET ...

Page 125: ...er on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value default value if not set most lately set when VV bit 1 After power on and the occurrence of a hard reset the host can issue this command only once when VV bit 1 If this command with VV bit 1 is is...

Page 126: ...mand requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password The password is retained by the device until the next power cycle The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed At command issuance I O regist...

Page 127: ...d sets the device into SET_MAX_LOCK state After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MAX ADDRESS command is not executed just bef...

Page 128: ... data transferred shall be compared with the stored password If the password compare fails the device returns command aborted and decrements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET MAX LOCK command the Unlock counter is set to a value of five When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the p...

Page 129: ...EZE LOCK command sets the device to SET_MAX_Frozen state After the device made a transition to the Set Max Freeze Lock state the following SET MAX commands are rejected then the device returns command aborted SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK If the Device is in the SET_MAX_UNLOCK state with the SET MAX FREEZE LOCK command then the device returns command aborted The ...

Page 130: ...C xx xx xx xx xx 1F1H ER Error information 17 READ NATIVE MAX ADDRESS F8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device sets the BSY bit and indicates the maximum address in the DH CH CL and SN registers Then it clears BSY and generates an interrupt At command issuance I O registers setting cont...

Page 131: ...evice 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status The device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not generate an interrupt A diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is d...

Page 132: ...lure of device 1 attention The device responds to this command with the result of power on diagnostic test At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 0 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H C...

Page 133: ...umber of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command At command issuance I O registers setting contents 1F7H CM 0 0 1 0 0 0 1 R 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 01 xx R Retry At command completion I O registers contents to be read 1F7H ST Status in...

Page 134: ... Same address issues sequence After READ LONG is issued WRITE LONG can be issued consecutively If above condition is not satisfied the WRITE LONG Data becomes the Uncorrectable error for subsequence READ command At command issuance I O registers setting contents 1F7H CM 0 0 1 1 0 0 1 R 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA ...

Page 135: ...ice sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1F7H CM 1 1 1 1 0 1 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H ...

Page 136: ...clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read...

Page 137: ... standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdown after completion of the command executio...

Page 138: ...of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status informat...

Page 139: ... starts the countdown when the device returns to idle mode When the timer value reaches 0 a specified time has padded the device enters standby mode Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting content...

Page 140: ...nd generates an interrupt This command does not support the automatic power down sequence At command issuance I O registers setting contents 1F7H CM X 94 or X E0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error in...

Page 141: ...d the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7H CM X 99 or X E6 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx ...

Page 142: ...s the BSY bit and generates an interrupt Power save mode Sector Count register During moving to standby mode Standby mode During returning from the standby mode X 00 Idle mode X FF Active mode X FF At command issuance I O registers setting contents 1F7H CM X 98 or X E5 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read...

Page 143: ...rs 4Fh in the CL register and C2h in the CH register If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the FR register set to D8h If the failure prediction function is enabled the device collects and updates data on specif...

Page 144: ...turned on or off If the automatic attribute save function is enabled and more than 15 minutes has elapsed since the last time that attributes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device asserts BSY enables or disables the automatic attribute save function and clears BSY X ...

Page 145: ...ub command asserts the BSY bit and when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN SC Log sector 80h 9Fh 01h 10h Host vendor log The host can write any desired data in the host vendor log X D8 SMART Enable Operations This subcommand enables the failu...

Page 146: ...ssed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART Read Attribute Values subcommand FR register D0h SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device ...

Page 147: ...4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following table 5 8 The host can access this data using the SMART Read Attribute Values subcommand FR register D0h The insurance failure threshold value data is 512 byte data the format of this data is shown the following table 5 9 The host can access this data using the SMART Read...

Page 148: ...n time sec 16E Reserved 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 9 Format of insurance failure threshold valu...

Page 149: ...te ID The attribute ID is defined as follows Attribute ID Attribute name 0 Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Tempera...

Page 150: ...aved even if the drive fault prediction function is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the ultra ATA CRC error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with ...

Page 151: ...Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft hard reset from the host 3h Self test cannot be executed 4h Self test...

Page 152: ...indicates that the SMART Off line Read Scanning Technology is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 to 7 Reserved bits Failure prediction capability flag Bit Meaning 0 If this bit is 1 it indicates that the attribute value is saved on media before the drive enters the power save mode 1 If this bit is 1 it indicates that the attribute value is sa...

Page 153: ... Address 81h Address 9Fh 102 and 13F are both the same format as 100 101 140 1FF Reserved SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table and the SMART Comprehensive Error Log see Table and saves the information on media The host issues the SMART...

Page 154: ...to 3D Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error register value 40 Sector Count register value 41 Sector Number register value 42 Cylinder Low register value 43 Cylinder High register value 44 Drive Head register value 45 Status register value 46 to 58 Vendor unique 59 State 5A 5B Error log data structure Error data structure Power on time unit h 5...

Page 155: ...e Bits 4 to 7 Vendor unique Status Meaning 0 Unclear status 1 Sleep status 2 Standby status 3 Active status or idle status BSY bit 0 4 Off line data collection being executed 5 to F Reserved Table 5 11 1 Data format of SMART Comprehensive Error Log Byte First sector Next sector 00h SMART Error Logging 01h Reserved 01h Index Pointer Latest Error Data Structure Reserved 02h 5Bh 1 st Error Log Data S...

Page 156: ... Self test log 1 Self test number SN Register Value 03 Self test execution status 04 05 Life time Total power on time hours 06 Self test error No 07 to 0A Error LBA 0B to 19 Vendor unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test ...

Page 157: ...lready set and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while...

Page 158: ...words Bits 1 to 15 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 1 0 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information ...

Page 159: ...x 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 32 SECURITY ERASE UNIT F4h This command erases all user data This command also invalidates the user password and releases the lock function The host transfers the 512 byte data shown...

Page 160: ...orted Command error At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 0 0 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 33 SECURITY FREEZE LOCK F5h This command puts the device into FROZEN MODE The ...

Page 161: ...error The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ LONG READ MULTIPLE EXT READ SECTORS READ VERIFY SECTORS WRITE DMA EXT WRITE LONG WRITE MULTIPLE EXT WRITE SECTORS EXT WRITE VERIFY SECURITY DISABLE PASSWORD SECURITY FREEZE LOCK SECURITY SET PASSWORD SET MAX ADDRESS EXT FLUSH CACHE EXT DCO RESTORE DCO SET SET MAX ADDRESS ...

Page 162: ...14 to the device The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data Table 5 15 Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error Table 5 14 Contents of SECURITY SET PASSWORD data Word Contents 0 Control word Bit 0 Identifier 0 Sets a user password 1 Sets a m...

Page 163: ...unction is not enabled User Maximum The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password only The master password already set cannot cancel LOCKED MODE Master Maximum The specified password is saved as a new master password The lock function is not enabled At command issuan...

Page 164: ... password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT com...

Page 165: ...ery error recovery so that the data are read correctly When executing this command the reading of the data may take several seconds if much data are to be read In case a non recoverable error has occurred while the data is being read the error generation address is put into the command block register before ending the command This error sector is deleted from the write cache data and the remaining...

Page 166: ...e value placed in the Features register The following table shows these Features register values If this command sets with the reserved value of Features register an aborted error is posted FR values Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved At command issuance I O register conten...

Page 167: ...ice power down or reset If a Host Protected Area has been set by a SET MAX ADDRESS EXT command or if DEVICE CONFIGURATION FREEZE LOCK is set an aborted error is posted DEVICE CONFIGURATION FREEZE LOCK FR C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK comm...

Page 168: ...d by the device is described in Table 5 16 The DEVICE CONFIGURATION SET command transfers an overlay that modifies some of the bits set in words 63 82 83 84 and 88 of the IDENTIFY DEVICE command response When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the ove...

Page 169: ...e supported Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 X 00CF Command set feature set supported Bit 15 9 Reserved Bit 8 1 48 bit Addressing feature set supported Bit 7 1 Host Protected Area feature set supported Bit 6 1 Automatic acoustic management supported Bit 5 1 READ WRITE DMA QUEUED commands supported Bit 4 1 Power up in S...

Page 170: ...registers setting contents 1F7h CM 0 0 0 1 0 1 1 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C xx xx xx xx xx xx xx xx xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h ...

Page 171: ... bit is 1 the highest address value is defined as the last value specified If the VV bit is not set to 1 the highest address is the default value After a power on reset is performed a host can issue the SET MAX ADDRESS EXT command only once if the VV bit is 1 If the SET MAX ADDRESS EXT command is issued twice or more an ID Not Found error occurs When the SET MAX ADDRESS EXT command is executed all...

Page 172: ...ious At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0 1F1h ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information 0 HOB 0 1 HOB 1 40 FLUSH CACHE EXT EAH Description This command executes th...

Page 173: ...4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C xx xx xx xx xx xx xx xx xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0 1F1h ER xx xx xx xx xx xx xx xx Error information 0 HOB 0 1 HOB 1 ...

Page 174: ...e I O registers setting contents 1F7h CM 0 0 1 1 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1...

Page 175: ...nce I O registers setting contents 1F7h CM 0 0 1 0 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx...

Page 176: ... issuance I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1...

Page 177: ...nd issuance I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L...

Page 178: ... issuance I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1...

Page 179: ...nd issuance I O registers setting contents 1F7h CM 0 0 1 0 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L...

Page 180: ...DMA V V V V V V WRITE VERIFY V V V V V V READ VERIFY SECTOR S V V V V V V RECALIBRATE V V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETERS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V SET MAX ADDRESS V V V V V READ NATIVE MAX ADDRESS V V V V EXECUTE DEVICE DIAGNOSTIC 1 1 1 1 1 V READ LONG V V V V V WRITE LONG V V V V V READ BUFFER V V ...

Page 181: ... V V V SECURITY FREEZE LOCK V V V V SECURITY SET PASSWORD V V V V SECURITY UNLOCK V V V V FLUSH CACHE V V V V V DEVICE CONFIGURATION V V V V READ NATIVE MAX ADDRESS EXT V V V V SET MAX ADDRESS EXT V V V V V FLUSH CACHE EXT V V V V V READ SECTOR S EXT V V V V V V WRITE SECTOR S EXT V V V V V READ MULTIPLE EXT V V V V V V WRITE MULTIPLE EXT V V V V V READ DMA EXT V 2 V V V V V V WRITE DMA EXT V 2 V ...

Page 182: ...e READ LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer to t...

Page 183: ...g Figure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Figure 5 3 Read Sector s command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the ...

Page 184: ... operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed Figure 5 4 Protocol for command abort 5 4 2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S EXT WRITE LONG WRITE BUFFER WRITE...

Page 185: ...hen the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit d The host writes one sector of data through the Data register e The device clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the D...

Page 186: ...ost does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guarante...

Page 187: ...EXT IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS SECURITY ERASE PREPARE SECURITY FREEZE LOCK FLUSH CACHE EXT Figure 5 6 shows the protocol for the command execution without data transfer Figure 5 6 Protocol for the command execution without data transfe...

Page 188: ... EXT WRITE DMA EXT Starting the DMA transfer command is the same as the READ SECTOR S or WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol ...

Page 189: ...e DMA channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit or DRQ bit during DMA data transfer f When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal The...

Page 190: ...Interface 5 114 C141 E171 03EN g d f f d e Figure 5 7 Normal DMA data transfer ...

Page 191: ...or an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data Words in the IDENTIFY DE...

Page 192: ...ltra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 3 Ultra DMA data in commands 5 5 3 1 Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless o...

Page 193: ...The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements 1 The device shall drive a data word onto DD 15 0 2 The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more fre...

Page 194: ...l be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tRFS timing for the device 5 The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise spec...

Page 195: ... host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 12 The device shall release DSTROBE within tIORDYZ after the host negates DMACK 13 The host shall not negate STOP no assert HDMARDY until at least tACK after negating DMACK 14...

Page 196: ...MARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 10 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and ...

Page 197: ...host has asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst 8 The host shall negate STOP within tENV after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE 9 The device shall assert DDMARDY within tLI after the host has negated STOP After asserting DM...

Page 198: ...DMA burst by not generating an HSTROBE edge Note The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tRP before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HSTROBE edg...

Page 199: ...after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated 6 The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 7 The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has n...

Page 200: ...e shall not assert DMARQ again until after the Ultra DMA burst is terminated 6 The host shall assert STOP with tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 7 If HSTROBE is negated the host shall assert HSTROBE with tLI after the device has negated DMARQ No data shall be transferred during this assertion The device shall i...

Page 201: ...hall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a...

Page 202: ...ollowing table describes recommended values for series termination at the host and the device Table 5 17 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 22 ohm 82 ohm DIOW STOP 22 ohm 82 ohm CS0 CS1 33 ohm 82 ohm DA0 DA1 DA2 33 ohm 82 ohm DMACK 22 ohm 82 ohm DD15 through DD0 33 ohm 47 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm IORDY DDM...

Page 203: ...t1 Data register selection setup time for DIOR DIOW 25 ns t2 Pulse width of DIOR DIOW 70 ns t2i Recovery time of DIOR DIOW 25 ns t3 Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 50 ns t6 Data hold time for DIOR 5 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns...

Page 204: ...IOW tI Symbol Timing parameter Min Max Unit t0 Cycle time 120 ns tD Pulse width of DIOR DIOW 70 ns tE Data Access time for DIOR 50 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOR DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns t CS 1 0 Available time for DIOR DIOW 25 ns Figure 5 10 Multiword DMA data transfer timing mode 2 ...

Page 205: ...1 Initiating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 11 Initiating an Ultra DMA data in burst DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tUI tENV tFS tENV tZAD t...

Page 206: ... 4 6 Data hold time at recipient from STROBE edge until data may become invalid 2 5 tDVS 70 48 31 20 6 7 4 8 Data valid setup time at sender from data valid until STROBE edge 3 tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Data valid hold time at sender from STROBE edge until data may become invalid 3 tCS 15 10 7 7 5 5 CRC word setup time at device 2 tCH 5 5 5 5 5 5 CRC word hold time device 2 tCVS 70 48 31 20 6 7...

Page 207: ...on or negation tSS 50 50 50 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst 1 Except for some instances of tMLI that apply to host signals only the parameters tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before p...

Page 208: ...2 tDVHIC 9 9 9 9 9 6 Sender IC data valid hold time from STROBE edge until data may become invalid 2 1 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at tDSIC and tDHIC timing as measured through 1 5V 2 The parameters tDVSIC and tDVHIC shall be met for lu...

Page 209: ...e to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 12 Sustained Ultra DMA data in burst DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host t2CYC tCYC tDVS tDVSIC tDVH tDVHIC tDS tDSIC tDH tDHIC t2CYC tCYC tDVS tDVSIC tDVH tDVHIC t...

Page 210: ...tes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device Figure 5 13 Host pausing an Ultra DMA data in burst tRP tRFS DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device ...

Page 211: ...the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Device terminating an Ultra DMA data in burst DMARQ device DMACK host DD 15 0 HDMARDY host DSTROBE device STOP host DA0 DA1 DA2 CS0 CS1 tMLI tLI tLI tLI tACK tACK tIORDYZ tSS tZAH tAZ tCVS tCVH CRC tACK ...

Page 212: ...MA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Host terminating an Ultra DMA data in burst DMARQ device tLI tMLI tRP tZAH tAZ tRFS tLI tMLI tCVS tCVH tACK tACK tACK tIORDYZ CRC DA0 DA1 DA2 CS0 CS1 DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 ...

Page 213: ...h of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 16 Initiating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tUI tLI tACK tACK tDVH tDVS tDZFS ...

Page 214: ...hasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 17 Sustained Ultra DMA data out burst HSTROBE at host HSTROBE at device DD 15 0 at host DD 15 0 at device t2CYC tCYC tCYC t2CYC tDVH tDVHIC tDVS tDVSIC tDVS tDVSIC tDVH tDVHIC tDH tDHIC tDS tDSIC tDH tDHI...

Page 215: ...Modes Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Figure 5 18 Device pausing an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tRP tRFS ...

Page 216: ...tra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Host terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tLI tLI tSS tLI tMLI tACK tIORDYZ tACK tACK tCVH tCVS CRC DA0 DA1 DA2 CS0 CS1 ...

Page 217: ...he Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Device terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tLI tLI tRP tRFS tMLI tMLI tCVS tCVH tIORDYZ tACK tACK tACK CRC ...

Page 218: ...re reset 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP asse...

Page 219: ...C141 E171 03EN 6 1 CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Power Save 6 3 Defect Processing 6 4 Read Ahead Cache 6 5 Write Cache ...

Page 220: ...firms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report...

Page 221: ...ore the device power is turned on 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 450 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the mas...

Page 222: ...ted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received Max 31 sec Max 400 ms Max 30 sec Max 1 ms If presence of a slave device is confirmed PDIAG is checked for up to 31 seconds Checks DASP for up to 450 ms DASP PDIAG BSY bit Reset Status Reg BSY bit Slave device Master device Figure 6 2 Response to hardware reset Note Master Devic...

Page 223: ... report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If t...

Page 224: ...he self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds The asserted PDIAG signal is negated 5 seconds after it is asserted if the command is not received If the command is received the PDIAG signal is negated according to timing at which the command is received When the IDD is set to a slave device the IDD asserts the DASP signal ...

Page 225: ...1 Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device enters the Active idle mode under the following conditions After completion of t...

Page 226: ...as elapsed in the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETE...

Page 227: ...edia defect location information is registered in the system space specified for the user area according to the format at shipment of the media from the plant 6 3 1 Spare area The following two types of areas are prepared as the spare area in user areas 1 Spare area for sector slip At shipment of the media from the plant this area is defined for use in alternating processing for defective sectors ...

Page 228: ...le where sector physical 5 with cylinder 0 and head 0 is defective Sector physical Cylinder 0 Head 0 Defec tive sector Not used Note When an access request for sector 5 is issued physical sector 6 must be accessed instead of physical sector 5 Figure 6 5 Sector slip processing 2 Alternate cylinder assignment processing This technology assigns a defective sector to a spare sector of an alternate cyl...

Page 229: ...tinue processing Figure 6 6 Alternate cylinder assignment processing 3 Automatic alternating processing This device performs automatic alternating processing in the event of any of the following errors Automatic alternating processing is attempted for read error recovery by heightening the ECC correction capability while a read error retry is in progress Before attempting automatic alternating pro...

Page 230: ... command See Figure 6 7 For MPU work For R W command 2048 KB 2097152 bytes 0 5 KB 512 bytes 1984 KB 2031616 bytes 63 5 KB 65024 bytes For MPU work Figure 6 7 Data buffer structure The read ahead operation is performed while the READ SECTOR S or READ MULTIPLE or READ DMA command is in progress Read ahead data is stored in the read cache part of the buffer 6 4 2 Caching operation The caching operati...

Page 231: ...ata required by a command that is a target of caching and has been sent to the host system once If the sector data requested by the host has not been completely stored in the read cache portion of the buffer this data does not become a target of caching Also if sequential hits occur continuously the caching target data required by the host becomes invalid 3 Invalidating caching target data Data th...

Page 232: ...RD SECURITY UNLOCK SECURITY ERASE UNIT SECURITY DISABLE PASSWORD DEVICE CONFIGURATION IDENTITY DEVICE CONFIGURATION SET 2 The caching operation is invalidated by the SET FEATURES command 3 A soft hard reset is issued or the power is turned off 4 When a shift is made to the power saving mode at the Low Power Idle level or lower 5 When the above commands are aborted READ DMA READ MULTIPLE READ SECTO...

Page 233: ...dress point are defined in the sequential address of the segment that is read last Read segment DAP disk address pointer HAP host address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Read requested data is stored until this point Free space DAP HAP 3 When reading of read requested data is completed and tr...

Page 234: ...ial command 1 When the sequential read command is received DAP and HAP are set in the sequential address of the last read command and read requested data is read Free space Hit error data DAP HAP 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Hit error data Free space HAP DAP 3 When reading of read requested data i...

Page 235: ... the free space that has been made available by the data transfer 1 The following state is established when the read command is received START LBA LAST LBA DAP HAP being consecutive after the last set of read requested data Hit data Read ahead data 2 At the same time as a transfer of hit data starts reading of read ahead data is started for as many spaces as are made available by the transfer DAP ...

Page 236: ...mmand is received during the read ahead operation a transfer of the read requested data starts while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read comman...

Page 237: ...Remaining part of insufficient data is read then An example is a case where a partial hit occurs in cache data as shown below LAST LBA Cache valid data START LBA 1 HAP is set at the address where partial hit data is stored DAP is then set to the address immediately after the partial hit data HAP DAP Partial hit data Insufficient data 2 At the same time as a transfer of the partial hit data starts ...

Page 238: ...owever the caching operation is not performed when the caching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector ...

Page 239: ...in the system area of media System area information is loaded whenever the power is turned on 5 Reset response When a reset is received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This is true for both a hard reset and soft reset IMPORTANT If Write Cache is enabled there is a possibility that data transferred...

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Page 241: ... The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command ...

Page 242: ...e spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean dela...

Page 243: ...rmation posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly ...

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Page 245: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed ...

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Page 247: ...burst 5 139 device response 6 2 to reset 6 2 device terminating Ultra DMA data in burst 5 135 5 141 out burst 5 141 E enabling and disabling 6 21 F fluctuation current 1 7 full hit 6 18 H hit full 6 18 hit no 6 15 hit partial 6 19 hit sequential 6 17 host pausing Ultra DMA data in burst 5 134 host terminating Ultra DMA data in burst 5 136 out burst 5 140 I initiaitng Ultra DMA data in burst 5 129 ...

Page 248: ...reset 6 3 power on 6 2 software reset 6 5 S sector slip processing 6 10 sequential command 6 16 sequential hit 6 17 sequential reading 6 16 sleep mode 6 8 spare area 6 9 standby mode 6 8 status report in event of error 6 20 sustain Ultra DMA data in burst 5 133 out burst 5 138 sustained Ultra DMA data in burst 5 133 out burst 5 138 T terminating device Ultra DMA data out burst 5 135 5 141 terminat...

Page 249: ...d F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo 144 0...

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Page 251: ...MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES PRODUCT MANUAL C141 E171 03EN MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES PRODUCT MANUAL C141 E171 03EN ...

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