Fujitsu MHS2020AT, Product Manual, Page: 189 / 254

5.4 Command Protocol
C141-E171-03EN 5-113
The interrupt processing for the DMA transfer differs the following point.
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The interrupt processing for the DMA transfer differs the following point.
a) The host writes any parameters to the Features, Sector Count, Sector
Number, Cylinder, and Device/Head register.
b) The host initializes the DMA channel
c) The host writes a command code in the Command register.
d) The device sets the BSY bit of the Status register.
e) The device asserts the DMARQ signal after completing the preparation of
data transfer. The device asserts either the BSY bit or DRQ bit during DMA
data transfer.
f) When the command execution is completed, the device clears both BSY and
DRQ bits and asserts the INTRQ signal. Then, the host reads the Status
register.
g) The host resets the DMA channel.
Figure 5.7 shows the correct DMA data transfer protocol.