5.3 Host Commands
C141-E171-03EN
5-95
(39) SET MAX ADDRESS EXT (37H)
•
Description
This command limits specifications so that the highest address that can be
accessed by users can be specified only in LBA mode.
The address information specified with this command is set in words 1, 54,
57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command
response. If read or write processing is executed for an address that is
outside of the new address space, an ID Not Found error occurs.
If the SC register bit is 0 and the value volatile (VV) bit is 1 when this
command is executed, the specified values are maintained after a power-on
reset. If the VV bit is 0 when the command is executed, the specified values
are invalidated during the power-on sequence. If the VV bit is 1, the highest
address value is defined as the last value specified. (If the VV bit is not set to
1, the highest address is the default value.)
After a power-on reset is performed, a host can issue the SET MAX
ADDRESS (EXT) command only once if the VV bit is 1. If the SET MAX
ADDRESS (EXT) command is issued twice or more, an ID Not Found error
occurs.
When the SET MAX ADDRESS EXT command is executed, all SET MAX
ADDRESS commands are aborted. The address value returns to the origin
when the SET MAX ADDRESS EXT command is executed using the
address value returned by the READ NATIVE MAX ADDRESS command.
•
Error reporting conditions
−
This command is issued twice or more in an operation sequence. (ST =
51h, ER = 10h, ID Not Found)
−
The READ NATIVE MAX ADDRESS EXT command (27h) is not
issued immediately before this command (ST = 51h, ER = 04h, Aborted)
is issued.
−
This command is issued while LBA = 0 (ST = 51h, ER = 04h, Aborted)
−
The SET MAX ADDRESS command has already been issued.
Summary of Contents for MHS2020AT
Page 1: ...C141 E171 03EN MHS2060AT MHS2040AT MHS2030AT MHS2020AT DISK DRIVES PRODUCT MANUAL ...
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Page 60: ...Theory of Device Operation 4 6 C141 E171 03EN Figure 4 3 Circuit Configuration ...
Page 190: ...Interface 5 114 C141 E171 03EN g d f f d e Figure 5 7 Normal DMA data transfer ...
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