Fujitsu MHS2020AT, Product Manual, Page: 89 / 254

5.2 Logical Interface
C141-E171-03EN 5-13
- Bit 1: Always 0.
- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the
previous command was being executed. The Error register indicates
the additional information of the cause for the error.
(10) Command register (X’1F7’)
The Command register contains a command code being sent to the device. After
this register is written, the command execution starts immediately.
Table 5.3 lists the executable commands and their command codes. This table
also lists the necessary parameters for each command which are written to certain
registers before the Command register is written.
5.2.3 Control block registers
(1) Alternate Status register (X’3F6’)
The Alternate Status register contains the same information as the Status register
of the command block register.
The only difference from the Status register is that a read of this register does not
imply Interrupt Acknowledge and INTRQ signal is not reset.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ 0 0 ERR