Freescale Semiconductor KKL02Z32CAF4R, Reference Manual

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Clock name Description
Clocks the bus slaves and peripherals.
Flash clock Flash memory clock
On this device, it is the same as Bus clock.
MCGIRCLK MCG output of the slow or fast internal reference clock
MCGOUTCLK MCG output of either IRC, MCGFLLCLK or MCG's external
reference clock that sources the core, system, bus, and flash
clock.
MCGFLLCLK MCG output of the FLL
MCGFLLCLK may clock some modules. In addition,
this clock is used for UART0 and TPM modules.
OSCCLK System oscillator output of the internal oscillator or sourced
directly from EXTAL. Used as MCG external reference clock.
OSCERCLK System oscillator output sourced from OSCCLK that may
clock some on-chip modules
ERCLK32K Clock source for some modules that is chosen as
OSC32KCLK
LPO PMC 1 kHz output
5.4.1 Device clock summary
The following table provides more information regarding the on-chip clocks.
Table 5-1. Clock summary
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
MCGOUTCLK Up to 48 MHz Up to 4 MHz MCG In all stop modes
except for partial stop
modes.
MCGFLLCLK Up to 48 MHz N/A MCG MCG clock controls are
not enabled and in all
stop modes
Core clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider In all wait and stop
modes
Platform clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider In all stop modes
System clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider In all stop modes and
Compute Operation
Bus clock Up to 24 MHz Up to 1 MHz
1
MCGOUTCLK clock
divider In all stop modes
except for partial
STOP2 mode, and
Compute Operation
SWD Clock Up to 24 MHz Up to 1 MHz SWD_CLK pin In all stop modes
Table continues on the next page...
Chapter 5 Clock Distribution
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc. 87