27.2.1 TPM_EXTCLK — TPM External Clock
The rising edge of the external input signal is used to increment the TPM counter if
selected by CMOD[1:0] bits in the SC register. This input signal must be less than half of
the TPM counter clock frequency. The TPM counter prescaler selection and settings are
also used when an external input is selected.
27.2.2 TPM_CHn — TPM Channel (n) I/O Pin
Each TPM channel can be configured to operate either as input or output. The direction
associated with each channel, input or output, is selected according to the mode assigned
for that channel.
27.3 Memory Map and Register Definition
This section provides a detailed description of all TPM registers.
Attempting to access a reserved register location in the TPM memory map will generate a
bus error.
TPM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_8000 Status and Control (TPM0_SC)
32
R/W
0000_0000h
4003_8004 Counter (TPM0_CNT)
32
R/W
0000_0000h
4003_8008 Modulo (TPM0_MOD)
32
R/W
0000_FFFFh
4003_800C Channel (n) Status and Control (TPM0_C0SC)
32
R/W
0000_0000h
4003_8010 Channel (n) Value (TPM0_C0V)
32
R/W
0000_0000h
4003_8014 Channel (n) Status and Control (TPM0_C1SC)
32
R/W
0000_0000h
4003_8018 Channel (n) Value (TPM0_C1V)
32
R/W
0000_0000h
4003_8050 Capture and Compare Status (TPM0_STATUS)
32
R/W
0000_0000h
4003_8084 Configuration (TPM0_CONF)
32
R/W
0000_0000h
4003_9000 Status and Control (TPM1_SC)
32
R/W
0000_0000h
4003_9004 Counter (TPM1_CNT)
32
R/W
0000_0000h
4003_9008 Modulo (TPM1_MOD)
32
R/W
0000_FFFFh
4003_900C Channel (n) Status and Control (TPM1_C0SC)
32
R/W
0000_0000h
4003_9010 Channel (n) Value (TPM1_C0V)
32
R/W
0000_0000h
4003_9014 Channel (n) Status and Control (TPM1_C1SC)
32
R/W
0000_0000h
4003_9018 Channel (n) Value (TPM1_C1V)
32
R/W
0000_0000h
Table continues on the next page...
Memory Map and Register Definition
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
412
Freescale Semiconductor, Inc.
