• Resides between a crossbar switch slave port and a peripheral bridge bus controller
• Two-stage pipeline design matching the AHB system bus protocol
• Combinationally passes non-decorated accesses to peripheral bridge bus controller
• Conversion of decorated loads and stores from processor core into atomic read-
modify-writes
• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit
operations
• Decorated stores support bit field inserts, logical AND, OR, and XOR operations
• Support for byte, halfword and word-sized decorated operations
• Supports minimum signal toggling on AHB output bus to reduce power dissipation
16.1.3 Modes of operation
The BME module does not support any special modes of operation. As a memory-
mapped device located on a crossbar slave AHB system bus port, BME responds strictly
on the basis of memory addresses for accesses to the connected peripheral bridge bus
controller.
All functionality associated with the BME module resides in the core platform's clock
domain; this includes its connections with the crossbar slave port and the PBRIDGE bus
controller.
16.2 External signal description
The BME module does not directly support any external interfaces.
The internal interfaces include two standard AHB buses with 32-bit datapath widths: the
primary input from the appropriate crossbar slave port (mx_h<signal>) and the primary
output to the PBRIDGE bus controller (sx_h<signal>).
Note the signal directions are defined by the BME's view and are labeled based on the
dominant direction. Accordingly, the mx_h<signal> AHB bus is the primary input, even
though there are certain data phase signals (mx_h{rdata, ready, resp}) which are outputs
from BME. Likewise, the sx_h<signal> AHB bus is the primary output even though there
are specific data phase signals (sx_h{rdata, ready, resp}) which are inputs to BME.
Chapter 16 Bit Manipulation Engine (BME)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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