Freescale Semiconductor ColdFire MCF5211, Reference Manual

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Interrupt Controller Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
12-6 Freescale Semiconductor
12.3 Register Descriptions
The interrupt controller registers are described in the following sections.
12.3.1 Interrupt Pending Registers (IPRH n , IPRL n )
The IPRH n and IPRL n registers, Figure 12-1 and Figure 12-2 , each 32 bits, provide a bit map for each
interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given
source. The state of the interrupt mask register does not affect the IPR
n . The IPR n is cleared by reset. The
IPR n is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and
reads as a zero.
0x0FF8 GL6IACK Reserved
0x0FFC GL7IACK Reserved
IPSBAR
Offset: 0x0C00 (IPRH n )
Access: Read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R INT[63:48]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R INT[47:32]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-1. Interrupt Pending Register High (IPRH n )
Table 12-3. IPRH n Field Descriptions
Field Description
31–0
INT
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRH n bit determines whether an
interrupt condition can generate an interrupt. At every system clock, the IPRH n samples the signal generated by the
interrupting source. The corresponding IPRH n bit reflects the state of the interrupt signal even if the corresponding
IMRH n bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Table 12-2. Interrupt Controller Memory Map (continued)
Module Offset Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0]