Clock Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual
,
Rev. 3
6-8
Freescale Semiconductor
Table 6-6. SYNSR Field Descriptions
Field
Description
7
EXTOSC
Indicates if an external oscillator is providing the reference clock source
0) Reference clock is not external oscillator
1 Reference clock is external oscillator
6
OCOSC
Indicates if the on-chip oscillator is providing the reference clock source.
0 Reference clock is not on-chip oscillator
1 Reference clock is on-chip oscillator
5
CRYOSC
Indicates if an external crystal is providing the reference clock source
0 Reference clock is not external crystal
1 Crystal clock reference
4
LOCKS
Sticky indication of PLL lock status.
0 PLL loss of lock since last system reset or MFD change or currently not locked due to exit from STOP
with FWKUP set
1 No unintentional PLL loss of lock since last system reset or MFD change
The lock detect function sets the LOCKS bit when the PLL achieves lock after:
• A system reset
• A write to SYNCR that changes the MFD[2:0] bits
When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains cleared until one of
the two listed events occurs.
In stop mode, if the PLL is intentionally disabled, then the LOCKS bit reflects the value prior to entering stop
mode. However, if FWKUP is set, then LOCKS is cleared until the PLL regains lock. after lock is regained,
the LOCKS bit reflects the value prior to entering stop mode. Furthermore, reading the LOCKS bit at the
same time that the PLL loses lock does not return the current loss of lock condition.
In external clock mode, LOCKS remains cleared after reset. In normal PLL mode
and 1:1 PLL mode
,
LOCKS is set after reset.
3
LOCK
Set when the PLL is locked. PLL lock occurs when the synthesized frequency is within approximately 0.75%
of the programmed frequency. The PLL loses lock when a frequency deviation of greater than approximately
1.5% occurs. Reading the LOCK flag at the same time that the PLL loses lock or acquires lock does not
return the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a condition for
releasing reset.
If operating in external clock mode, LOCK remains cleared after reset.
0 PLL not locked
1 PLL locked
