Pulse-Width Modulation (PWM) Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
24-9
24.2.9
PWM Channel Counter Registers (PWMCNT
n
)
Each channel has a dedicated 8-bit up/down counter that runs at the rate of the selected clock source,
PWMCLK[PCLK
n
]. The user can read the counters at any time without affecting the count or the
operation of the PWM channel. In left-aligned output mode, the counter counts from 0 to the value in the
period register minus 1. In center-aligned output mode, the counter counts from 0 up to the value in the
period register and then back down to 0. Therefore, given the same value in the period register,
center-aligned mode is twice the period of left-aligned mode.
Any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up
for center-aligned mode, the immediate load of duty and period registers with values from the buffers, and
the output to change according to the polarity bit.
The counter is also cleared at the end of the effective period (see
Section 24.3.2.5, “Left-Aligned Outputs”
and
Section 24.3.2.6, “Center-Aligned Outputs”
for more details). When the channel is disabled
(PWME
n
=0), the PWMCNT
n
register does not count. When a channel is enabled (PWME
n
=1), the
associated PWM counter starts at the count in the PWMCNT
n
register. For more detailed information on
the operation of the counters, refer to
Section 24.3.2.4, “PWM Timer Counters.”
Table 24-9. PWMSCLB Field Descriptions
Field
Description
7–0
SCALEB
Divisor used to form Clock SB from Clock B.
IPSBAR
Offset:
0x1B_000C (PWMCNT0)
0x1B_000D (PWMCNT1)
0x1B_000E (PWMCNT2)
0x1B_000F (PWMCNT3)
0x1B_0010 (PWMCNT4)
0x1B_0011 (PWMCNT5)
0x1B_0012 (PWMCNT6)
0x1B_0013 (PWMCNT7)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
COUNT
W
Reset:
0
0
0
0
0
0
0
0
Figure 24-10. PWM Counter Registers (PWMCNT
n
)
SCALEB
Value
0x00
256
0x01
1
0x02
2
...
...
0xFF
255
