Freescale Semiconductor ColdFire MCF5211, Reference Manual

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MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor xxix
• Chapter 20, “Queued Serial Peripheral Interface (QSPI),” provides a feature-set overview and a
description of operation, including details of the QSPI’s internal storage organization. The chapter
concludes with the programming model and a timing diagram.
• Chapter 21, “UART Modules,” describes the use of the universal asynchronous
receiver/transmitters (UARTs) implemented on the device and includes programming examples.
• Chapter 22, “I
2
C Interface,” describes the I
2
C module, including I
2
C protocol, clock
synchronization, and I
2
C programming model registers.
• Chapter 23, “Analog-to-Digital Converter (ADC) ,” describes the two separate and complete
ADCs, each with their own sample and hold circuits and a common voltage reference and common
digital control module.
• Chapter 24, “Pulse-Width Modulation (PWM) Module ,” describes the configuration and operation
of the pulse width modulation (PWM) module. It includes a block diagram, programming model,
and functional description.
• Chapter 25, “FlexCAN ,” describes the implementation of the controller area network (CAN)
protocol. It describes FlexCAN module operation and provides a programming model.
• Chapter 26, “Debug Module,” describes the hardware debug support in the device.
• Chapter 27, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the
Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE
1149.1 standard and provides additional information specific to the device. For internal details and
sample applications, see the IEEE 1149.1 document.
• Appendix A, “Register Memory Map Quick Reference ,” summarizes the address, name, and byte
assignment for registers within the CPU space, lists an overview of the memory map for the
on-chip modules, and provides a detailed memory map including all of the registers for on-chip
modules.
Additional literature is published as new processors become available. For a current list of ColdFire
documentation, refer to
http://www.freescale.com/coldfire .
Conventions
This document uses the following notational conventions:
cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MNEMONICS In text, instruction mnemonics are shown in uppercase.
mnemonics In code and tables, instruction mnemonics are shown in lowercase.
italics Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number
REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.