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Freescale Semiconductor ColdFire MCF5211, Reference Manual

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Queued Serial Peripheral Interface (QSPI)

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

20-4

Freescale Semiconductor

 

Table 20-3. QMR Field Descriptions

Field

Description

15

MSTR

Master mode enable. 
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.

14

DOHIE

Data output high impedance enable. Selects QSPI_DOUT mode of operation.
0 Default value after reset. QSPI_DOUT is actively driven between transfers.
1 QSPI_DOUT is high impedance between transfers.

13–10

BITS

Transfer size. Determines the number of bits to be transferred for each entry in the queue. 

9

CPOL

Clock polarity. Defines the clock polarity of QSPI_CLK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.

8

CPHA

Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.

7–0

BAUD

Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI. 
A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and 
QMR[BAUD] by the following expression:

QMR[BAUD] = f

sys/

/ (2 ×

[desired QSPI_CLK baud rate])

BITS

Bits per Transfer

0000

16

0001–0111

Reserved

1000

8

1001

9

1010

10

1011

11

1100

12

1101

13

1110

14

1111

15

Summary of Contents for ColdFire MCF5211

Page 1: ...MCF5213 ColdFire Integrated Microcontroller Reference Manual Devices Supported MCF5211 MCF5212 MCF5213 Document Number MCF5213RM Rev 3 03 2007...

Page 2: ...r purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limit...

Page 3: ...M General Purpose I O Module Interrupt Controller Module Edge Port Module EPORT DMA Controller Module ColdFire Flash Module CFM EzPort Programmable Interrupt Timers PIT0 PIT1 General Purpose Timer Mod...

Page 4: ...dule SCM General Purpose I O Module Interrupt Controller Module Edge Port Module EPORT DMA Controller Module ColdFire Flash Module CFM EzPort Programmable Interrupt Timers PIT0 PIT1 General Purpose Ti...

Page 5: ...1 4 1 4 1 V2 Core Overview 1 8 1 4 2 Integrated Debug Module 1 9 1 4 3 JTAG 1 9 1 4 4 On Chip Memories 1 10 1 4 4 1 SRAM 1 10 1 4 4 2 Flash Memory 1 10 1 4 5 Power Management 1 10 1 4 6 FlexCAN 1 10...

Page 6: ...als 2 10 2 15 EzPort Signal Descriptions 2 12 2 16 Power and Ground Pins 2 12 Chapter 3 ColdFire Core 3 1 Processor Pipelines 3 1 3 2 Memory Map Register Description 3 2 3 2 1 Data Registers D0 D7 3 4...

Page 7: ...n Execution Times 3 21 3 6 4 Standard Two Operand Instruction Execution Times 3 22 3 6 5 Miscellaneous Instruction Execution Times 3 23 3 6 6 MAC Instruction Execution Times 3 24 3 6 7 Branch Instruct...

Page 8: ...on 6 1 6 3 1 Normal PLL Mode 6 1 6 3 2 1 1 PLL Mode 6 2 6 3 3 External Clock Mode 6 2 6 4 Low Power Mode Operation 6 2 6 5 Block Diagram 6 2 6 6 Signal Descriptions 6 4 6 6 1 EXTAL 6 4 6 6 2 XTAL 6 4...

Page 9: ...ment Register Low PPMRL 7 4 7 2 2 Low Power Interrupt Control Register LPICR 7 5 7 2 3 Peripheral Power Management Set Register PPMRS 7 7 7 2 4 Peripheral Power Management Clear Register PPMRC 7 7 7 2...

Page 10: ...State During Low Power Modes 7 17 Chapter 8 Chip Configuration Module CCM 8 1 Introduction 8 1 8 1 1 Features 8 1 8 2 External Signal Descriptions 8 1 8 2 1 RCON 8 2 8 2 2 CLKMOD 1 0 8 2 8 2 3 JTAG_E...

Page 11: ...8 9 6 3 1 Reset Flow 9 8 9 6 3 2 Reset Status Flags 9 9 Chapter 10 System Control Module SCM 10 1 Introduction 10 1 10 2 Overview 10 1 10 3 Features 10 1 10 4 Memory Map and Register Definition 10 2...

Page 12: ...SETn 11 7 11 6 4 Port Clear Output Data Registers CLRn 11 9 11 6 5 Pin Assignment Registers 11 10 11 6 5 1 Dual Function Pin Assignment Registers 11 11 11 6 5 2 Quad Function Pin Assignment Registers...

Page 13: ...ers 13 3 13 4 1 Memory Map 13 3 13 4 2 Registers 13 3 13 4 2 1 EPORT Pin Assignment Register EPPAR 13 4 13 4 2 2 EPORT Data Direction Register EPDDR 13 4 13 4 2 3 Edge Port Interrupt Enable Register E...

Page 14: ...criptions 15 7 15 3 3 1 CFMMCR CFM Module Configuration Register 15 7 15 3 3 2 CFMCLKD CFM Clock Divider Register 15 8 15 3 3 3 CFMSEC CFM Security Register 15 9 15 3 3 4 CFMPROT CFM Protection Regist...

Page 15: ...n 16 1 16 3 External Signal Description 16 2 16 3 1 Overview 16 2 16 3 2 Detailed Signal Descriptions 16 2 16 3 2 1 EZPCK EzPort Clock 16 2 16 3 2 2 EZPCS EzPort Chip Select 16 3 16 3 2 3 EZPD EzPort...

Page 16: ...r 18 General Purpose Timer Module GPT 18 1 Introduction 18 1 18 2 Features 18 1 18 3 Block Diagram 18 2 18 4 Low Power Mode Operation 18 3 18 5 Signal Description 18 3 18 5 1 GPT 2 0 18 3 18 5 2 GPT3...

Page 17: ...7 6 Gated Time Accumulation Mode 18 18 18 7 7 General Purpose I O Ports 18 19 18 8 Reset 18 21 18 9 Interrupts 18 21 18 9 1 GPT Channel Interrupts CnF 18 21 18 9 2 Pulse Accumulator Overflow PAOVF 18...

Page 18: ...r QDLYR 20 5 20 3 3 QSPI Wrap Register QWR 20 6 20 3 4 QSPI Interrupt Register QIR 20 6 20 3 5 QSPI Address Register QAR 20 7 20 3 6 QSPI Data Register QDR 20 8 20 3 7 Command RAM Registers QCR0 QCR15...

Page 19: ...Description 21 16 21 4 1 Transmitter Receiver Clock Source 21 16 21 4 1 1 Programmable Divider 21 17 21 4 1 2 Calculating Baud Rates 21 17 21 4 1 2 1 Internal Bus Clock Baud Rates 21 17 21 4 1 2 2 Ext...

Page 20: ...and Clock Stretching 22 12 22 4 Initialization Application Information 22 12 22 4 1 Initialization Sequence 22 12 22 4 2 Generation of START 22 12 22 4 3 Post Transfer Software Response 22 13 22 4 4 G...

Page 21: ...nd Control 23 30 23 5 7 Interrupt Sources 23 32 23 5 8 Power Management 23 32 23 5 8 1 Power Management Modes 23 32 23 5 8 2 Power Management Details 23 33 23 5 8 3 ADC STOP Mode of Operation 23 34 23...

Page 22: ...5 Left Aligned Outputs 24 17 24 3 2 5 1 Left Aligned Output Example 24 17 24 3 2 6 Center Aligned Outputs 24 18 24 3 2 6 1 Center Aligned Output Example 24 19 24 3 2 7 PWM 16 Bit Functions 24 19 24 3...

Page 23: ...nd Releasing Message Buffers 25 24 25 3 17 CAN Protocol Related Frames 25 25 25 3 17 1 Remote Frames 25 25 25 3 17 2 Overload Frames 25 25 25 3 18 Time Stamp 25 26 25 3 19 Bit Timing 25 26 25 4 Initia...

Page 24: ...Fill Memory Block fill 26 32 26 5 3 3 7 Resume Execution go 26 33 26 5 3 3 8 No Operation nop 26 34 26 5 3 3 9 Synchronize PC to the PST DDATA Lines sync_pc 26 34 26 5 3 3 10 Read Control Register rc...

Page 25: ...27 4 27 3 3 Bypass Register 27 5 27 3 4 JTAG_CFM_CLKDIV Register 27 5 27 3 5 TEST_CTRL Register 27 5 27 3 6 Boundary Scan Register 27 6 27 4 Functional Description 27 6 27 4 1 JTAG Module 27 6 27 4 2...

Page 26: ...MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 xxvi Freescale Semiconductor Contents Paragraph Number Title Page Number...

Page 27: ...for system software and hardware developers and applications programmers who want to develop products with the MCF5213 It is assumed that the reader understands operating systems microprocessor system...

Page 28: ...ller module It provides an overview of the module and describes in detail its signals and registers The latter sections of this chapter describe operations features and supported data transfer modes i...

Page 29: ...the device Chapter 27 IEEE 1149 1 Test Access Port JTAG describes configuration and operation of the Joint Test Action Group JTAG implementation It describes those items required by the IEEE 1149 1 st...

Page 30: ...olarity of the indicated signal The following register fields are used 1 The only exceptions to this appear in the discussion of serial communication modules that support variable length data transmis...

Page 31: ...access DSP Digital signal processing EA Effective address FIFO First in first out GPIO General purpose I O I2 C Inter integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP In...

Page 32: ...ransmit UART Universal asynchronous synchronous receiver transmitter Table ii Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition example NE for not equal Register S...

Page 33: ...tructions identifies an indirect data address referencing memory xxx identifies an absolute address referencing memory dn Signal displacement value n bits wide example d16 is a 16 bit displacement SF...

Page 34: ...e instruction performs no operation Refer to the Bcc instruction description as an example Subfields and Qualifiers Optional operation Identifies an indirect address dn Displacement value n bits wide...

Page 35: ...ontrol applications This 32 bit device is based on the Version 2 V2 ColdFire reduced instruction set computing RISC core with a multiply accumulate unit MAC and divider providing 76 Dhrystone 2 1 MIPS...

Page 36: ...FlexCAN 2 0B Module See note1 1 FlexCAN is available on the MCF5211 only in the 64 QFN package Four channel Direct Memory Access DMA Watchdog Timer Module WDT Programmable Interval Timer Module PIT 2...

Page 37: ...2 Part Number Summary Arbiter Interrupt Controller UART 0 QSPI UART 1 UART 2 I2 C DTIM 0 DTIM 1 DTIM 2 DTIM 3 V2 ColdFire CPU IFP OEP MAC 4 CH DMA MUX JTAG TAP To From PADI 32 Kbytes SRAM 4K 16 4 256...

Page 38: ...ecode that allows for 68K emulation support System debug support Real time trace for determining dynamic execution path Background debug mode BDM for in circuit debugging DEBUG_B Real time debug suppo...

Page 39: ...related addressing No read write semaphores Three programmable mask registers global for MBs 0 13 special for MB14 and special for MB15 Programmable transmit first scheme lowest ID or lowest buffer n...

Page 40: ...ns resolution at 80 MHz Programmable sources for clock input including an external clock option Programmable prescaler Input capture capability with programmable trigger edge on input pin Output compa...

Page 41: ...can be clocked from PLL or directly from crystal oscillator or relaxation oscillator Low power modes supported 2n n 0 15 low power divider for extremely low frequency operation Interrupt controller Un...

Page 42: ...ssor core is comprised of two separate pipelines that are decoupled by an instruction buffer The two stage instruction fetch pipeline IFP is responsible for instruction address generation and instruct...

Page 43: ...outines to be serviced while processing a debug interrupt event thereby ensuring that the system continues to operate even during debugging To support program trace the V2 debug module provides proces...

Page 44: ...ingle chip applications allowing for field reprogramming without requiring an external high voltage source The CFM interfaces to the ColdFire core through an optimized read only memory controller whic...

Page 45: ...epeatedly until manually stopped The ADC can be configured for either sequential or simultaneous conversion When configured for sequential conversions up to eight channels can be sampled and stored in...

Page 46: ...its PIT modulus register or it can be a free running down counter 1 2 14 Pulse Width Modulation PWM Timers The MCF5213 has an 8 channel 8 bit PWM timer Each channel has a programmable period and duty...

Page 47: ...ware explicitly setting a DCRn START bit or by the occurrence of certain UART or DMA timer events 1 2 19 Reset The reset controller determines the source of reset asserts the appropriate reset signals...

Page 48: ...Overview MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 1 14 Freescale Semiconductor...

Page 49: ...tput defines its state at reset and identifies whether a pull up resistor should be used NOTE The terms assertion and negation are used to avoid confusion when dealing with a mixture of active low and...

Page 50: ...2 DTIM 3 V2 ColdFire CPU IFP OEP MAC 4 CH DMA MUX JTAG TAP To From PADI 32 Kbytes SRAM 4K 16 4 256 Kbytes Flash 32K 16 4 PORTS GPIO CIM RSTI RSTO UTXDn URXDn URTSn DTINn DTOUTn CANRX JTAG_EN ADC AN 7...

Page 51: ...4 AN5 GPIO Low FAST 53 G8 35 AN4 GPIO Low FAST 54 F9 36 AN3 GPIO Low FAST 46 G7 28 AN2 GPIO Low FAST 45 G6 27 AN1 GPIO Low FAST 44 H6 26 AN0 GPIO Low FAST 43 J6 25 SYNCA N A N A No Primary SYNCB N A N...

Page 52: ...C7 44 TDI DSI N A N A pull up5 79 B7 50 TDO DSO High FAST 80 A7 51 TMS BKPT N A N A pull up5 76 A8 49 TRST DSCLK N A N A pull up5 85 B6 54 Mode Selection6 CLKMOD0 N A N A pull down6 40 G5 24 CLKMOD1...

Page 53: ...PDSR 23 PSRR 23 pull up9 62 D8 43 GPT2 PWM5 GPIO PDSR 22 PSRR 22 pull up9 61 D9 42 GPT1 PWM3 GPIO PDSR 21 PSRR 21 pull up9 59 E9 41 GPT0 PWM1 GPIO PDSR 20 PSRR 20 pull up9 58 F7 40 Timers 32 bit DTIN3...

Page 54: ...ogrammable signals default to 2 mA drive and FAST slew rate in normal single chip mode 2 All signals have a pull up in GPIO mode 3 The multiplexed CANTX and CANRX signals are not available on the MCF5...

Page 55: ...PLL and Clock Signals Signal Name Abbreviation Function I O External Clock In EXTAL Crystal oscillator or external clock input except when the on chip relaxation oscillator is used I Crystal XTAL Cry...

Page 56: ...ormal mode clock driven by crystal Table 2 6 External Interrupt Signals Signal Name Abbreviation Function I O External Interrupts IRQ 7 1 External interrupt sources I Table 2 7 Queued Serial Periphera...

Page 57: ...ction I O Transmit Serial Data Output UTXDn Transmitter serial data outputs for the UART modules The output is held high mark condition when the transmitter is disabled idle or in the local loopback m...

Page 58: ...ce VRH Reference voltage high and low inputs I VRL I Analog Supply VDDA Isolate the ADC circuitry from power supply noise VSSA Table 2 12 GPT Signals Signal Name Abbreviation Function I O General Purp...

Page 59: ...r the serial communication port to the debug module after the DSCLK has been seen as high logic 1 I Development Serial Output DSO Development Serial Output Provides serial output communication for deb...

Page 60: ...nal Name Abbreviation Function I O EzPort Clock EZPCK Shift clock for EzPort transfers I EzPort Chip Select EZPCS Chip select for signaling the start and end of serial transfers I EzPort Serial Data I...

Page 61: ...wo separate pipelines decoupled by an instruction buffer The instruction fetch pipeline IFP is a two stage pipeline for prefetching instructions The prefetched instruction stream is then gated into th...

Page 62: ...ter to register and register to memory store operations the instruction passes through both OEP stages once For memory to register and read modify write memory operations an instruction is effectively...

Page 63: ...tore 0x181 Data Register 1 D1 32 R W 0x10A0_1070 No 3 2 1 3 4 Load 0x082 7 Store 0x182 7 Data Register 2 7 D2 D7 32 R W Undefined No 3 2 1 3 4 Load 0x088 8E Store 0x188 8E Address Register 0 6 A0 A6 3...

Page 64: ...r stack pointer USP The hardware implementation of these two programmable visible 32 bit registers does not identify one as the SSP and the other as the USP Instead 0xC05 RAM Base Address Register RAM...

Page 65: ...e to load store the USP move l Ay USP move to USP move l USP Ax move from USP These instructions are described in the ColdFire Family Programmer s Reference Manual NOTE The USP must be initialized usi...

Page 66: ...re BDM LSB of Status Register SR Access User read write BDM read write 7 6 5 4 3 2 1 0 R 0 0 0 X N Z V C W Reset 0 0 0 Figure 3 5 Condition Code Register CCR Table 3 2 CCR Field Descriptions Field Des...

Page 67: ...licitly after reset and before any compare CMP Bcc or Scc instructions execute BDM 0x801 VBR Access Supervisor read write BDM read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 68: ...ision ISA_A Instruction Description BITREV The contents of the destination data register are bit reversed that is new Dn 31 equals old Dn 0 new Dn 30 equals old Dn 1 new Dn 0 equals old Dn 31 BYTEREV...

Page 69: ...The IACK cycle is mapped to special locations within the interrupt controller s address space with the interrupt level encoded in the address 3 The processor saves the current context by creating an...

Page 70: ...the 16 bit format vector word F V and the 16 bit status register and the second longword contains the 32 bit program counter address Table 3 5 Exception Vector Assignments Vector Number s Vector Offs...

Page 71: ...the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt See Table 3 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 72: ...ction that generated the write Accordingly the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled All programming model updates...

Page 73: ...ectively ColdFire cores do not provide illegal instruction detection on the extension words on any instruction including MOVEC 3 5 4 Divide By Zero Attempting to divide by zero causes an exception vec...

Page 74: ...nd the SR reflects the value loaded in the previous step If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets SR T hardware loads the SR and generates...

Page 75: ...field defines a valid type the processor 1 reloads the SR operand 2 fetches the second longword operand 3 adjusts the stack pointer by adding the format value to the auto incremented address after the...

Page 76: ...ecuted the processor enters the fault on fault halted state ColdFire processors load hardware configuration information into the D0 and D1 general purpose registers after system reset The hardware con...

Page 77: ...resent in core This is the value used for this device 1 FPU execute engine is present in core 11 MMU MMU present This bit signals if the optional virtual memory management unit MMU is present in proce...

Page 78: ...f 0x0 indicating a 16 byte cache line size 29 28 CCAS Configurable cache associativity 00 Four way 01 Direct mapped This is the value used for this device Else Reserved for future use 27 24 CCSZ Confi...

Page 79: ...ction execution This implies that the OEP does not wait for the IFP to supply opwords and or extension words The OEP does not experience any sequence related pipeline stalls The most common example of...

Page 80: ...on Execution Times Table 3 12 lists execution times for MOVE B W instructions Table 3 13 lists timings for MOVE L NOTE For all tables in this section the execution time of any instruction using the PC...

Page 81: ...1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 Ay 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 Ay 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1...

Page 82: ...Operand Instruction Execution Times Opcode EA Effective Address Rn An An An d16 An d16 PC d8 An Xn SF d8 PC Xn SF xxx wl xxx add l ea Rx 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 add l Dy ea 3...

Page 83: ...l Dy ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 eori l imm Dx 1 0 0 lea ea Ax 1 0 0 1 0 0 2 0 0 1 0 0 lsl l ea Dx 1 0 0 1 0 0 lsr l ea Dx 1 0 0 1 0 0 moveq l imm Dx 1 0 0 or l ea Rx 1 0 0 3 1 0 3 1...

Page 84: ...3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 wdebug ea 5 2 0 5 2 0 1 n is the number of registers moved by the MOVEM opcode 2 If a MOVE W imm SR instruction is executed and imm 13 equals 1 the execution time i...

Page 85: ...Dx 5 0 0 7 1 0 7 1 0 7 1 0 7 1 0 muls w ea y Dx 3 0 0 5 1 0 5 1 0 5 1 0 5 1 0 6 1 0 5 1 0 3 0 0 mulu l ea y Dx 5 0 0 7 1 0 7 1 0 7 1 0 7 1 0 mulu w ea y Dx 3 0 0 5 1 0 5 1 0 5 1 0 5 1 0 6 1 0 5 1 0 3...

Page 86: ...ire Integrated Microcontroller Reference Manual Rev 3 3 26 Freescale Semiconductor Table 3 19 Bcc Instruction Execution Times Opcode Forward Taken Forward Not Taken Backward Taken Backward Not Taken b...

Page 87: ...oint fractional operands 3 Miscellaneous register operations The MAC features a three stage execution pipeline optimized for 16 bit operands with a 16x16 multiply array and a single 32 bit accumulator...

Page 88: ...eral Operation The MAC speeds execution of ColdFire integer multiply instructions MULS and MULU and provides additional functionality for multiply accumulate operations By executing MULS and MULU in t...

Page 89: ...ter application with auto increment addressing mode supports efficient implementation of circular data queues for memory operands 4 4 Memory Map Register Definition The following table and sections ex...

Page 90: ...to a general purpose register See Section 4 4 1 1 1 Rounding The resulting 16 bit value is stored in the lower word of the destination register The upper word is zero filled This rounding procedure do...

Page 91: ...the following example involving the rounding of a 32 bit number R0 to a 16 bit number Using this method the 32 bit number is rounded to the closest 16 bit number possible Let the high order 16 bits of...

Page 92: ...The following assembly language routine shows the proper sequence for a correct MAC state save This code assumes all Dn and An registers are available for use and the memory location of the state save...

Page 93: ...ion or any routine that implements a data array as a circular queue For MAC MOVE operations the MASK contents can optionally be included in all memory effective address calculations The syntax is as f...

Page 94: ...d Descriptions Field Description 31 0 Accumulator Store 32 bits of the result of the MAC operation Table 4 6 MAC Instruction Summary Command Mnemonic Description Multiply Signed muls ea y Dx Multiplie...

Page 95: ...number that can be represented is 1 whose internal representation is 0x8000 and 0x8000_0000 respectively The largest positive word is 0x7FFF or 1 2 15 the most positive longword is 0x7FFF_FFFF or 1 2...

Page 96: ...o the lsb position The following pseudocode explains basic MAC or MSAC instruction functionality This example is presented as a case statement covering the three basic operating modes with signed inte...

Page 97: ...lse result 31 0 0x7fff_ffff else product 31 0 product 30 0 0 break case 2 reserved encoding break case 3 SF 1 if MACSR OMC 0 MACSR V 0 then product 31 0 product 31 product 31 1 break combine with accu...

Page 98: ...orm convergent rounding if product 31 0 0x8000_0000 then product 63 32 product 63 32 1 else if product 31 0 0x8000_0000 product 32 1 then product 63 32 product 63 32 1 combine with accumulator if inst...

Page 99: ...overflow MACSR V 1 if inst MSAC MACSR OMC 1 then result 31 0 0x0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMode enabled result 31 0 0xffff_ffff scale product before combining with accu...

Page 100: ...ulation overflow if accumulationOverflow 1 then MACSR V 1 if inst MSAC MACSR OMC 1 then result 31 0 0x0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMode enabled result 31 0 0xffff_ffff t...

Page 101: ...e SRAM module is physically connected to the processor s high speed local bus it can service processor initiated accesses or memory referencing commands from the debug module The SRAM is dual ported t...

Page 102: ...e g DMA access to the SRAM The RAMBAR contains several control fields These fields are shown in Figure 5 1 Table 5 1 SRAM Programming Model Rc 11 0 1 1 The values listed in this column represent the R...

Page 103: ...is set any attempted write access from the core generateS an access error exception to the ColdFire processor core 0 Allows core read and write accesses to the SRAM module 1 Allows only core read acc...

Page 104: ...RAM at 0x2000_0000 and initializes the SRAM to zeros RAMBASE EQU 0x20000000 set this variable to 0x20000000 RAMVALID EQU 0x00000001 move l RAMBASE RAMVALID D0 load RAMBASE valid bit into D0 movec l D0...

Page 105: ...tures Features of the clock module include the following 1 to 16 MHz crystal 8 MHz on chip relaxation oscillator or external oscillator reference options 2 to 10 MHz reference crystal oscillator for n...

Page 106: ...recovery time The PLL can be disabled in stop mode but requires a wakeup period before it can relock The oscillator can also be disabled during stop mode but requires a wakeup period to restart When...

Page 107: ...vider LPD 3 0 Reference Clock 0 0 1 1 FlexCAN oscillator clock ADC auto standby clock OSCILLATOR ON CHIP 8MHz OSCILLATOR PPRMH 11 CFM PPRMH 10 FlexCAN PPRMH 9 PWM PPRMH 8 GPT PPRMH 7 ADC PPRMH 4 3 PPR...

Page 108: ...clocking mode 6 6 3 CLKOUT This output reflects the internal system clock 6 6 4 CLKMOD 1 0 These inputs are used to select the clock mode during chip configuration as described in Table 6 3 Table 6 2...

Page 109: ...set1 1 Addresses not assigned to a register and undefined register bits are reserved for expansion Register Width bits Access Reset Value Section Page Supervisor Mode Access Only 0x12_0000 Synthesizer...

Page 110: ...the system manages a loss of clock condition When the LOCEN bit is clear LOCRE has no effect If the LOCS flag in SYNSR indicates a loss of clock condition setting the LOCRE bit causes an immediate res...

Page 111: ...ce clock is to drive the system clock This bit is ignored when the PLL is disabled in which case the PLL reference clock drives the system clock Having this separate bit allows the PLL to first be ena...

Page 112: ...changes the MFD 2 0 bits When the PLL loses lock LOCKS is cleared When the PLL relocks LOCKS remains cleared until one of the two listed events occurs In stop mode if the PLL is intentionally disabled...

Page 113: ...starts up During this time LOCS is temporarily set regardless of LOCEN It is cleared after the oscillator comes up and the PLL is attempting to lock If a read of the LOCS flag and a loss of clock cond...

Page 114: ...of lock condition occurs Table 6 9 shows the clock out frequency to clock in frequency relationships for the possible system clock modes The external clock is divided by two internally to produce the...

Page 115: ...Determine the appropriate value for the MFD and RFD fields in the SYNCR The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an RFD fa...

Page 116: ...feedback clock leads the falling edge of the reference clock the PFD pulses the DOWN signal The width of these pulses relative to the reference clock depends on how much the two clocks lead or lag eac...

Page 117: ...etermine when frequency lock is achieved Phase lock is inferred by the frequency relationship but is not guaranteed The LOCK flag in the SYNSR reflects the PLL lock status A sticky lock flag LOCKS is...

Page 118: ...the LOCKS flag reflects the value prior to entering stop mode after lock is regained 6 8 4 7 PLL Loss of Lock Reset If the LOLRE bit in the SYNCR is set a loss of lock condition asserts reset Reset r...

Page 119: ...ining operational clock The alternate clock source generates the system clocks until reset is asserted As Table 6 11 shows if the reference fails the PLL goes out of lock and into self clocked mode SC...

Page 120: ...k NRM 0 0 0 Off Off 0 Lose lock f b clock reference clock Regain NRM LK 1 LC No regain Stuck NRM X 0 0 Off Off 1 Lose lock f b clock reference clock Regain clocks but don t regain lock SCM unstable NR...

Page 121: ...M 0 0 0 On On 1 NRM LK 1 LC Lose lock Unstable NRM 0 0 1 LC Lose lock regain NRM 0 1 LC Lose clock Stuck Lose clock regain without lock Unstable NRM 0 0 1 LC Lose clock regain with lock NRM 0 1 LC NRM...

Page 122: ...ithout lock NRM 1 0 0 On On 0 NRM LK 1 LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f b clock REF 0 X 1 Wakeup without lock Lose lock Stuck Lose lock regain NRM 0 1 LC NRM 1 0 0 On On 1...

Page 123: ...ose lock regain NRM 0 1 LC NRM 1 1 1 On On X NRM LK 1 LC Lose clock or lock RESET Reset immediately REF 1 0 0 X X X REF 0 X 1 Lose reference clock Stuck SCM 1 0 0 Off X 0 PLL disabled Regain SCM SCM 0...

Page 124: ...rence mode due to losing PLL clock or lock from NRM mode SCM PLL self clocked mode due to losing reference clock from NRM mode RESET immediate reset LOCKS LK expecting previous value of LOCKS before e...

Page 125: ...ster Width bits Access Reset Value Section Page 0x11_0004 Chip Configuration Register CCR 2 2 The CCR is described in the Chip Configuration Module It is shown here only to warn against accidental wri...

Page 126: ...fundamental to the operation of the system the clocks for these three modules cannot be disabled The individual bits of the PPMRx can be modified using a read modify write to this register directly or...

Page 127: ...led 8 CDGPT Disable clock to the 16 bit general purpose timer module GPT 0 ICOC module clock is enabled 1 ICOC module clock is disabled 7 CDADC Disable clock to the ADC module 0 ADC module clock is en...

Page 128: ...0 0 Figure 7 2 Peripheral Power Management Register Low PPMRL Table 7 3 PPMRL Field Descriptions Field Description 31 18 Reserved should be cleared 17 CDINTC0 Disable clock to the INTC0 module 0 INTC...

Page 129: ...ICR is programmed setting the ENBSTOP bit if stop mode is the desired low power mode and loading the appropriate interrupt priority level 10 CDQSPI Disable clock to the QSPI module 0 QSPI module clock...

Page 130: ...r modes such as doze or wait fixed or programmable interrupts may be used however the module generating the interrupt must be enabled in that particular low power mode 5 After an appropriately high in...

Page 131: ...le without the need to perform a read modify write on the PPMRx The data value on a register write causes the corresponding bit in the PPMRx register to be cleared A data value of 64 to 127 provides a...

Page 132: ...cifies the low power mode entered when the STOP instruction is issued and controls clock activity in this low power mode IPSBAR Offset 0x0022 PPMRC Access write only 7 6 5 4 3 2 1 0 R 0 W PPMRC Reset...

Page 133: ...lect Used to select the low power mode the chip enters after the ColdFire CPU executes the STOP instruction These bits must be written prior to instruction execution for them to take effect The LPMD 1...

Page 134: ...al clocks appropriately During stop mode the system clock is stopped low For entry into stop mode the LPICR ENBSTOP bit must be set before a STOP instruction is issued IPSBAR Offset 0x0023 IPSBMT Acce...

Page 135: ...In this mode peripherals may be programmed to continue operating and can generate interrupts which cause the CPU to exit from wait mode 7 4 1 3 Doze Mode Doze mode affects the CPU in the same manner a...

Page 136: ...of low power mode via a core watchdog interrupt This system setup must meet the conditions specified in Section 7 4 1 Low Power Modes for the core watchdog interrupt to bring the part out of low powe...

Page 137: ...SPI is unaffected by wait mode and may generate an interrupt to exit this mode In stop mode the QSPI stops immediately and freezes operation register values state machines and external pins During thi...

Page 138: ...nal reset and exit any low power modes Registers lose current values and must be reconfigured from reset state if needed If the phase lock loop PLL in the clock module is active and if the appropriate...

Page 139: ...en in stop mode a recessive to dominant transition on the CAN bus causes the WAKE INT bit in the error status register to be set This event can cause a CPU interrupt if the WAKE MASK bit in module con...

Page 140: ...with Self Wake the user should disable all Tx sources including remote response before stop mode entry If halt mode is active at the time the STOP bit is set then the FlexCAN assumes that halt mode sh...

Page 141: ...g the external BKPT pin causes the CPU to exit any low power mode 7 4 2 20 JTAG The JTAG Joint Test Action Group controller logic is clocked using the TCLK input and is not affected by the system cloc...

Page 142: ...a interrupt that exits a low power mode The CPU begins to service the interrupt exception after wakeup Enabled Yes2 Enabled Yes2 I O Ports Enabled No Enabled No Enabled No Reset Controller Enabled Yes...

Page 143: ...ing Mode Serial flash programming mode EzPort mode Single chip mode Clock Reference External oscillator External crystal On chip 8 MHz oscillator Phase locked look PLL BDM or JTAG mode 8 2 External Si...

Page 144: ...used to select between debug module JTAG_EN 0 and JTAG JTAG_EN 1 modes at reset 8 2 4 TEST Reserved for factory testing only In normal modes of operation this pin must be connected to VSS to avoid uni...

Page 145: ...nly to warn against accidental writes to this register 8 R W 0x00 7 2 5 7 8 0x11_0008 Reset Configuration Register RCON 16 R 0x0000 8 3 3 2 8 4 0x11_000A Chip Identification Register CIR 16 R See note...

Page 146: ...8 5 RCON Field Descriptions Field Description 15 6 Reserved should be cleared 5 RLOAD Pad driver load This read only field reflects the reset value of the Pin Drive Strength Register If booting into E...

Page 147: ...Description Field Description 15 6 PIN Part identification number Contains a unique identification number for the device MCF5211 0x3C MCF5212 0x42 MCF5213 0x43 5 0 PRN Part revision number This numbe...

Page 148: ...Chip Configuration Module CCM MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 8 6 Freescale Semiconductor...

Page 149: ...s and resets is implemented within the reset controller module 9 2 Features Module features include the following Seven sources of reset External reset input Power on reset POR Watchdog timer Phase lo...

Page 150: ...ven low when the internal reset controller module resets the chip When RSTO is active the user can drive override options on the data bus 9 5 Memory Map and Registers The reset controller programming...

Page 151: ...ption 7 SOFTRST Allows software to request a reset The reset caused by setting this bit clears this bit 1 Software reset request 0 No software reset request 6 FRCRSTOUT Allows software to assert or ne...

Page 152: ...terrupt disabled 2 LVDRE LVD reset enable Controls the LVD reset if LVDE is set This bit has no effect if the LVDE bit is a logic 0 LVD reset has priority over LVD interrupt if both are enabled 1 LVD...

Page 153: ...complete Asynchronous reset sources usually indicate a catastrophic failure Therefore the reset control logic does not wait for the current bus cycle to complete Reset is asserted immediately to the s...

Page 154: ...Reset This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and the PLL reference or the PLL itself fails The reset controller asserts RSTO for approximately 512 cycles...

Page 155: ...STI PIN OR WD TIMEOUT OR SW RESET LOSS OF CLOCK LOSS OF LOCK RSTI NEGATED PLL MODE BUS CYCLE COMPLETE RCON ASSERTED PLL LOCKED ENABLE BUS MONITOR ASSERT RSTO AND LATCH RESET STATUS WAIT 512 CLKOUT CYC...

Page 156: ...or loss of lock 2 the reset control logic asserts RSTO 4 The reset control logic waits for the PLL to attain lock 9 9A before waiting 512 CLKOUT cycles 1 Then the reset control logic may latch the con...

Page 157: ...f lock condition is detected while waiting for the current bus cycle to complete 5 6 for an external reset request the EXT SOFT and or WDR bits along with the LOC and or LOL bits are set If the RSR bi...

Page 158: ...Reset Controller Module MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 9 10 Freescale Semiconductor...

Page 159: ...two memory banks one for the internal SRAM and the other for the internal flash The SACU provides the mechanism needed to implement secure bus transactions to the system address space The programming...

Page 160: ...Core Watchdog Control Register CWCR 8 R W 0x00 10 5 4 10 7 0x0012 Low Power Interrupt Control Register LPICR 8 R W 0x00 7 2 2 7 5 0x0013 Core Watchdog Service Register CWSR 8 R W 10 5 5 10 8 0x0014 D...

Page 161: ...Register 8 R W 0x00 10 7 3 3 10 16 0x0031 GPACR1 Register 8 R W 0x00 10 7 3 3 10 16 1 Addresses not assigned to a register and undefined register bits are reserved for expansion 2 The PPMRH LPICR PMRL...

Page 162: ...directly by the core and or other system bus masters Because this memory provides single cycle accesses at processor speed it is ideal for applications where double buffer schemes can be used to maxi...

Page 163: ...BAR is typically the same value however they can be programmed to different values By definition the base address must be a 0 modulo size value The SRAM modules are configured through the RAMBAR shown...

Page 164: ...reset is complete Only one bit is set at any one time in the CRSR The register reflects the cause of the most recent reset To clear a bit a logic 1 must be written to the bit location writing a zero h...

Page 165: ...nt the core watchdog timer from interrupting or resetting the CWSR must be serviced by performing the following sequence 1 Write 0x55 to CWSR 2 Write 0xAA to the CWSR Both writes must occur in order b...

Page 166: ...vior results Note If a core reset is required the watchdog interrupt should set the soft reset bit in the interrupt controller 5 3 CWT 2 0 Core watchdog timing delay These bits select the timeout peri...

Page 167: ...to by the current arbitration pointer may get on the bus with zero latency if the address phase is available All other requesters face at least a one cycle arbitration pipeline delay to meet bus timi...

Page 168: ...ansfer the master is given the lowest priority and the priority for all other masters is increased by one If no masters are requesting the arbitration unit must park pointing at one of the masters The...

Page 169: ...its bus requests 1 enable the use of the DMA s bandwidth control to elevate the priority of its bus requests 24 BCR24BIT Enables the use of 24 bit byte count registers in the DMA module 0 DMA BCRs fu...

Page 170: ...another set of control registers define the access levels associated with the peripheral modules and memory space The SACU s programming model is physically implemented as part of the system control...

Page 171: ...t This is intended to support the concept of a trusted bus master and also controls the ability of a bus master to modify the register state of any of the SACU control registers that is only trusted m...

Page 172: ...ccordingly MPR 0 is forced to 1 at reset 10 7 3 2 Peripheral Access Control Registers PACR0 PACR8 Access to several on chip peripherals is controlled by shared peripheral access control registers A si...

Page 173: ...tform peripheral The encodings for this field are shown in Table 10 11 3 LOCK0 This bit when set prevents subsequent writes to ACCESSCTRL0 Any attempted write to the PACR generates an error terminatio...

Page 174: ...specific GPACRn to be used for a given reference within the IPS address space These access control registers are 8 bits wide so that read write and execute attributes may be assigned to the given IPS...

Page 175: ...generates an error termination and the contents of the register are not affected Only a system reset clears this flag 6 4 Reserved should be cleared 3 0 ACCESS_CTRL This 4 bit field defines the acces...

Page 176: ...15 GPACR Address Space Register Space Protected IPSBAR Offset Modules Protected GPACR0 0x0000_0000 0x03FF_FFFF Ports CCM PMM Reset controller Clock EPORT WDOG PIT0 PIT3 QADC GPTA GPTB FlexCAN CFM Cont...

Page 177: ...Purpose I O Module Block Diagram DDATA 3 0 PDD 7 4 PORT QS PORT AS PORT DD PORT UA PORT UC PORT TC PORT TD PST 3 0 PDD 3 0 SDA PAS 1 CANRX RXD2 SCL PAS 0 CANTX TXD2 QSPI_SCK PQS 2 SCL RTS1 QSPI_DIN PQ...

Page 178: ...it DMA timers 11 3 Features The MCF5213 ports includes these distinctive features Control of primary function use on all ports Digital I O support for all ports registers for Storing output pin data C...

Page 179: ...eserved S U 0x10_0018 Reserved S U 0x10_001C DDRNQ DDRDD DDRAN DDRAS S U 0x10_0020 Reserved DDRQS DDRTA DDRTC S U 0x10_0024 DDRTD DDRUA DDRUB DDRUC S U Port Pin Data Set Data Registers 0x10_0028 Reser...

Page 180: ...Reading a PORTn register returns the current values in the register not the port n pin values PORTn bits can be set by setting the PORTn register or by setting the corresponding bits in the PORTnP SE...

Page 181: ...ead write At reset all bits in the DDRn registers are cleared IPSBAR Offset 0x10_000D PORTQS Access User read write 7 6 5 4 3 2 1 0 R 0 PORTn6 PORTn5 PORTn4 PORTn3 PORTn2 PORTn1 PORTn0 W Reset 0 1 1 1...

Page 182: ...lemented DDRDD DDRAN IPSBAR Offsets 0x10_0022 DDRTA 0x10_0023 DDRTC 0x10_0024 DDRTD 0x10_0025 DDRUA 0x10_0026 DDRUB 0x10_0027 DDRUC Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 DDRn3 DDRn2 DDRn1 D...

Page 183: ...ETn registers are set to the current pin states Reading a PORTnP SETn register returns the current state of the port n pins Writing 1s to a PORTnP SETn register sets the corresponding bits in the PORT...

Page 184: ...ORTTD SETTD PORTUA SETUA PORTUB SETUB PORTUC SETUC IPSBAR Offset 0x10_0035 PORTQSP SETQS Access User read write 7 6 5 4 3 2 1 0 R 0 PORTnP6 PORTnP5 PORTnP4 PORTnP3 PORTnP2 PORTnP1 PORTnP0 W Reset 0 1...

Page 185: ...sters The CLRn registers are read write Table 11 4 PORTnP SETn Field Descriptions Field Description PortnPx Port nx pin data set data bits 1 PortnPx pin state is 1 read writing a 1 sets the correspond...

Page 186: ...ser read write 7 6 5 4 3 2 1 0 R 0 CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 W Reset 0 0 0 0 0 0 0 0 Figure 11 19 Port QS Clear Output Data Register CLRQS IPSBAR Offset 0x10_0044 CLRNQ Access User rea...

Page 187: ...te 2 tertiary and GPIO quaternary functions The fields are described in Table 11 7 which applies to all quad function registers IPSBAR Offsets 0x10_0051 PDDPAR 0x10_0052 PANPAR Access User read write...

Page 188: ...R 0 0 0 0 PnPAR1 PnPAR0 W Reset 0 0 0 0 0 0 0 0 Figure 11 25 Port AS Pin Assignment Register PASPAR IPSBAR Offsets 0x10_0056 PTAPAR 0x10_0057 PTCPAR 0x10_0059 PUAPAR 0x10_005A PUBPAR Access User read...

Page 189: ...e described in Table 11 8 The slew rate control bits corresponding to each pin signal are listed in Table 2 1 on page 2 3 IPSBAR Offset 0x10_0050 PNQPAR Access User read write 7 6 5 4 3 2 1 0 R PNQPAR...

Page 190: ...r Reference Manual Rev 3 11 14 Freescale Semiconductor Table 11 8 PSRR Field Descriptions Field Description PSSRx PSSRx slew rate register control bits 1 Pin is configured for slow slew rate delay is...

Page 191: ...SR Access User read write 31 30 29 28 27 26 25 24 R PDSR31 PDSR30 PDSR29 PDSR28 PDSR27 PDSR26 PDSR25 PDSR24 W Reset See note 1 23 22 21 20 19 18 17 16 R PDSR23 PDSR22 PDSR21 PDSR20 PDSR19 PDSR18 PDSR1...

Page 192: ...General Purpose I O Module MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 11 16 Freescale Semiconductor...

Page 193: ...t architecture of the 68K ColdFire family is appropriate The interrupt architecture of ColdFire is exactly the same as the M68000 family where there is a 3 bit encoded interrupt priority level sent fr...

Page 194: ...he service routine For many peripheral devices the processing of the IACK cycle directly negates the interrupt request while other devices require that request to be explicitly negated during the proc...

Page 195: ...cognition phase 12 1 1 2 Interrupt Prioritization As an active request is detected it is translated into the programmed interrupt level and the resulting 7 bit decoded priority level IRQ 7 1 is driven...

Page 196: ...sts regardless of the complexity of the peripheral device 12 2 Memory Map The register programming model for the interrupt controllers is memory mapped to a 256 byte space In the following discussion...

Page 197: ...ICRn49 ICRn50 ICRn51 IPSBAR 0x0C74 ICRn52 ICRn53 ICRn54 ICRn55 IPSBAR 0x0C78 ICRn56 ICRn57 ICRn58 ICRn59 IPSBAR 0x0C7C ICRn60 ICRn61 ICRn62 ICRn63 IPSBAR 0x0C80 IPSBAR 0x0CDC Reserved IPSBAR 0x0CE0 S...

Page 198: ...Reserved IPSBAR Offset 0x0C00 IPRHn Access Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R INT 63 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INT 47...

Page 199: ...1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 2 Interrupt Pending Register Low IPRLn Table 12 4 IPRLn Field Descriptions Field Description 31 1 INT Interrupt Pending Each bit corresponds to a...

Page 200: ...upt signal even if the corresponding IMRHn bit is set 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked IPSBAR Offset 0x0C0C IMRLn Access Read write 31...

Page 201: ...ible source for functional or debug purposes The system design may reserve one or more sources to allow software to self schedule interrupts by forcing one or more of these bits 1 force request 0 nega...

Page 202: ...0 0 0 0 0 0 0 0 0 Figure 12 6 Interrupt Force Register Low INTFRCLn Table 12 8 INTFRCLn Field Descriptions Field Description 31 1 INTFRCL Interrupt force Allows software generation of interrupts for e...

Page 203: ...3 can be written Registers ICRn1 through ICRn7 are read only because the interrupt levels for IRQ1 through IRQ7 are hard coded see Section 12 1 1 Interrupt Controller Theory of Operation The registers...

Page 204: ...to program the ICRnx registers in this manner can result in undefined behavior If a specific interrupt request is completely unused the ICRnx value can remain in its reset and disabled state Figure 1...

Page 205: ...PF7 1 8 SCM SWTI Software watchdog timeout Cleared when service complete 9 DMA DONE DMA Channel 0 transfer complete Write DONE 1 10 DONE DMA Channel 1 transfer complete Write DONE 1 11 DONE DMA Channe...

Page 206: ...Message Buffer 12 Interrupt Write 1 to BUF12I after reading as 1 36 BUF13I Message Buffer 13 Interrupt Write 1 to BUF13I after reading as 1 37 BUF14I Message Buffer 14 Interrupt Write 1 to BUF14I afte...

Page 207: ...ssociated with interrupt exception processing including machine state save restore functions can be minimized In general the software IACK is performed near the end of an interrupt service routine and...

Page 208: ...3 2 1 0 R VECTOR W Reset 0 0 0 0 0 0 0 0 Figure 12 10 Software and Level m IACK Registers SWIACKn LmIACKn Table 12 14 SWIACKn and LmIACKn Field Descriptions Field Description 7 0 VECTOR Vector number...

Page 209: ...top mode LPICR 7 must be set to enable this mode of operation NOTE The wakeup mask level taken from LPICR 6 4 is adjusted by hardware to allow a level 7 IRQ to generate a wakeup That is the wakeup mas...

Page 210: ...Interrupt Controller Module MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 12 18 Freescale Semiconductor...

Page 211: ...h or a general purpose input output I O pin See Figure 13 1 Figure 13 1 EPORT Block Diagram 13 2 Low Power Mode Operation This section describes the operation of the EPORT module in low power modes Fo...

Page 212: ...n synchronizer is bypassed for the level detect logic because no clocks are available 13 3 Interrupt General Purpose I O Pin Descriptions All pins default to general purpose input pins at reset The pi...

Page 213: ...ach pin individually EPORT data register EPDR holds the data to be driven to the pins EPORT pin data register EPPDR reflects the current state of the pins EPORT flag register EPFR individually latches...

Page 214: ...To guarantee that a level sensitive interrupt request is acknowledged the interrupt source must keep the signal asserted until acknowledged by software Level sensitivity must be selected to bring the...

Page 215: ...served should be cleared IPSBAR Offset 0x13_0003 EPIER Access Supervisor read write 7 6 5 4 3 2 1 0 R EPIE7 0EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 0 W Reset 0 0 0 0 0 0 0 0 Figure 13 4 EPORT Port Interr...

Page 216: ...sets EPD7 EPD1 0 Reserved should be cleared IPSBAR Offset 0x13_0005 EPPDR Access User read only 7 6 5 4 3 2 1 0 R EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 0 W Reset Current pin state 0 Figure 13 6 EP...

Page 217: ...te bit in EPFR indicates that the selected edge has been detected Reset clears EPF7 EPF1 Bits in this register are set when the selected edge is detected on the corresponding pin A bit remains set unt...

Page 218: ...Edge Port Module EPORT MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 13 8 Freescale Semiconductor...

Page 219: ...d throughout this section to refer to registers or signals associated with one of the four identical DMA channels DMA0 DMA1 DMA2 or DMA3 14 1 1 Overview The DMA controller module enables fast transfer...

Page 220: ...address transfers Channel arbitration on transfer boundaries Data transfers in 8 16 32 or 128 bit blocks using a 16 byte buffer Continuous mode or cycle steal transfers Independent transfer widths for...

Page 221: ...al address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by a peripheral DMA request Two types of transfer can occur a read from a sour...

Page 222: ...0 BCR0 and DMA Status Register 0 DSR0 0x00_010C DMA Control Register 0 DCR0 1 0x00_0110 Source Address Register 1 SAR1 0x00_0114 Destination Address Register 1 DAR1 0x00_0118 Byte Count Register 1 BCR...

Page 223: ...nnection between the DMA requesters and that DMA channel There are ten possible requesters 4 DMA Timers and 6 UARTs Any request can be routed to any of the DMA channels Effectively the DMAREQC provide...

Page 224: ...oller writes to the appropriate DSRn bit Only a write to DSRn DONE results in action DSRn DONE is set when the block transfer is complete When a transfer sequence is initiated and BCRn BCR is not a mu...

Page 225: ...red 1 The DMA channel terminated with a bus error during the write portion of a transfer 3 Reserved should be cleared 2 REQ Request 0 No request is pending or the channel is currently active Cleared w...

Page 226: ...on 0 No interrupt is generated 1 Internal interrupt signal is enabled 30 EEXT Enable external request Care should be taken because a collision can occur between the START bit and DREQn when EEXT equal...

Page 227: ...19 DINC Destination increment Controls whether a destination address increments after each successful transfer 0 No change to the DAR after a successful transfer 1 The DAR increments by 1 2 4 or 16 d...

Page 228: ...D value is non zero the buffer base address is located on a boundary of the buffer size The value of this boundary depends on the initial destination address DAR The base address should be aligned to...

Page 229: ...el LCH1 after each cycle steal transfer followed by a link to LCH2 after the BCR decrements to zero 10 Perform a link to channel LCH1 after each cycle steal transfer 11 Perform a link to channel LCH1...

Page 230: ...ms the specified number of transfers then relinquishes bus control The DMA negates its internal bus request on the last transfer before BCRn reaches a multiple of the boundary specified in BWC Upon co...

Page 231: ...If the DCRn BWC value of sequential channels are equal the channels are prioritized in ascending order The DMAREQC register is configured to assign peripheral DMA requests to the individual DMA chann...

Page 232: ...formed on registers not chosen for alignment If BCRn is greater than 16 the address determines transfer size Bytes words or longwords are transferred until the address is aligned to the programmed siz...

Page 233: ...one of the following reasons Error conditions When the DMA encounters a read or write cycle that terminates with an error condition DSRn BES is set for a read and DSRn BED is set for a write before th...

Page 234: ...DMA Controller Module MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 14 16 Freescale Semiconductor...

Page 235: ...tes read operations to the flash memory using one or two system bus cycles to access each flash physical block with access latency depending on the factory setting of the CLKSEL bits in the CFMCLKSEL...

Page 236: ...d verify operations Single power supply for program and erase operations Software programmable interrupts on command completion access violations or protection violations Fast page erase operation Fas...

Page 237: ...addresses PROGRAM_ARRAY_BASE 0x0000_0000 to PROGRAM_ARRAY_BASE 0x0003_FFFF Figure 15 2 CFM Flash Memory Map The CFM has hardware interlocks that protect data from accidental corruption using program...

Page 238: ...ontains several control fields These fields are shown in Figure 15 3 NOTE The default value of the FLASHBAR is determined by the chip configuration selected at reset see Chapter 8 Chip Configuration M...

Page 239: ...ails When the default reset configuration is not overridden the MCU by default boots up in single chip mode and the flash space is marked as valid at address 0x0 The flash configuration field is check...

Page 240: ...cycle mask SC Supervisor code address space mask SD Supervisor data address space mask UC User code address space mask UD User data address space mask For each address space bit 0 An access to the fl...

Page 241: ...fer error IPSBAR Offset 0x1D_0000 CFMMCR Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 LOCK PVIE AEIE CBEI E CCIE KEYA CC 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F...

Page 242: ...register is set 1 An interrupt is requested when the CBEIF flag is set 0 CBEIF interrupt disabled 6 CCIE Command complete interrupt enable The CCIE bit is always readable and writable The CCIE bit ena...

Page 243: ...vely divides the internal flash bus clock down to a frequency of 150 KHz 200 KHz The internal flash bus clock frequency range is 150 KHz internal flash bus clock 102 4 MHz The CFMCLKD register bits PR...

Page 244: ...SEC bits define the security state of the MCU as shown in Table 15 7 which defines the single code that enables the security feature in the CFM Table 15 7 CFM Security States SEC 15 0 Description 0x4A...

Page 245: ...ion field must first be unprotected then the flash protection bytes must be programmed with the desired value PROTECT 31 0 Figure 15 8 CFMPROT Protection Diagram Table 15 8 CFMPROT Field Descriptions...

Page 246: ...flash configuration field must first be unprotected then the flash supervisor access bytes must be programmed with the desired value Each flash logical sector may be mapped into supervisor or unrestri...

Page 247: ...ion address space see Figure 15 8 for details on flash sector mapping 15 3 3 7 CFMUSTAT CFM User Status Register The CFMUSTAT register defines the flash command controller status and flash memory acce...

Page 248: ...re are no more commands pending The CCIF flag is cleared by the flash command controller when CBEIF is cleared and sets upon completion of all active and pending commands Writing to the CCIF flag has...

Page 249: ...NK flag has no effect on BLANK 1 All flash memory locations or selected logical page verify as erased 0 If a blank check or page erase verify command has been executed and the CCIF flag is set then a...

Page 250: ...tion c Program erase and verify operations Section 15 4 2 3 Program Erase and Verify Operations d Stop mode Section 15 4 2 4 Stop Mode 2 Flash security operation Section 15 4 3 Flash Security Operatio...

Page 251: ...internal flash bus clock via a programmable counter The command register as well as the associated address and data registers operate as a buffer and a register 2 stage FIFO so that a new command alon...

Page 252: ...command can be executed if the CFMCLKD register has not been written to Section 15 4 2 3 5 Flash Normal Mode Illegal Operations 15 4 2 3 2 Command Write Sequence The flash command controller is used t...

Page 253: ...command is shown in Figure 15 14 The blank check command write sequence is as follows 1 Write to any flash memory address to start the command write sequence for the blank check command The specific...

Page 254: ...er CFMUSTAT yes no Clear bit CBEIF 0x80 Clock Register Written Check 1 2 3 yes no Access Error and Protection Violation no and Data Bit Polling for Command Completion Check Read Register CFMUSTAT yes...

Page 255: ...r 3 Clear the CBEIF flag by writing a 1 to CBEIF to launch the page erase verify command Because the word addresses in even and odd flash blocks are interleaved pages from adjacent interleaving flash...

Page 256: ...Register CFMUSTAT yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read Register CFMUSTAT yes NOTE command write sequence aborted by writing 0x0...

Page 257: ...address The same relative address in multiple program flash physical blocks may be programmed simultaneously by writing to the relative address in flash physical block order even block odd block The f...

Page 258: ...es Clock Register Written Check 1 2 3 no Protection Violation Check Read Register CFMUSTAT CCIF Set Bit no no Address Data Command Buffer Empty Check Next Write yes no Data Clear bit PVIOL 0x20 Write...

Page 259: ...sh logical page to erase while the data written during the page erase command write sequence is ignored 2 Write the page erase command 40 to the CFMCMD register 3 Clear the CBEIF flag by writing a 1 t...

Page 260: ...egister Written Check 1 2 3 no Protection Violation Check Read Register CFMUSTAT CCIF Set Bit no no Address Data Command Buffer Empty Check Next Write yes no and Dummy Data Clear bit PVIOL 0x20 Write...

Page 261: ...and data written during the mass erase command write sequence is ignored 2 Write the mass erase command 41 to the CFMCMD register 3 Clear the CBEIF flag by writing a 1 to CBEIF to launch the mass eras...

Page 262: ...ion Check Read Register CFMUSTAT CCIF Set Bit no no Address Data Command Buffer Empty Check Next Write yes no Dummy Data Clear bit PVIOL 0x20 Write Register CFMUSTAT yes PVIOL Set Bit Bit Polling for...

Page 263: ...g after writing to the flash memory or after writing a command to the CFMCMD register but before the command is launched The PVIOL flag is set during the command write sequence if any of the following...

Page 264: ...o 32 bit writes to address 0x0400 and 0x0404 in that order The two backdoor write cycles can be separated by any number of internal flash bus cycles NOTE Any attempt to use a key of all zeros or all o...

Page 265: ...executed on the flash memory The CFM is unsecured if the blank check operation determines that the entire flash memory is erased After the next reset sequence the security state of the CFM is determin...

Page 266: ...ColdFire Flash Module CFM MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 15 32 Freescale Semiconductor...

Page 267: ...ogrammed like standard SPI flash memories available from ST Microelectronics Macronix Spansion and other vendors The EzPort implements the same command set as devices from these vendors so existing mi...

Page 268: ...EZPCK EzPort Clock EzPort clock EZPCK is the serial clock for data transfers Serial data in EZPD and chip select EZPCS are registered on the rising edge of EZPCK while serial data out EZPQ is driven...

Page 269: ...ers It is registered on the rising edge of EZPCK All commands addresses and data are shifted in most significant bit first When EzPort is driving output data on EZPQ the data shifted in EZPD is ignore...

Page 270: ...Offset Access read write 7 6 5 4 3 2 1 0 R FS WEF CRL WEN WIP W Reset 0 11 1 Reset value reflects if flash security is enabled or disabled out of reset 0 0 0 0 0 0 0 Figure 16 2 EzPort Status Registe...

Page 271: ...ion register has not been loaded erase and program commands are not accepted 1 Configuration register has been loaded erase and program commands are accepted 4 2 Reserved should be cleared 1 WEN Write...

Page 272: ...ot accepted if flash security is enabled 16 4 1 7 Page Program The Page Program command programs locations in flash memory that have previously been erased The starting address of the memory to progra...

Page 273: ...f the write error flag is set a write is in progress the write enable bit is not set or the configuration register has not been written 16 4 1 10 Reset Chip The Reset Chip command forces the chip into...

Page 274: ...ion register 1 If fSYS is greater than 25 6 MHz PRDIV8 1 otherwise PRDIV8 0 2 Determine DIV 5 0 by using the following equation Keep only the integer portion of the result and discard any fraction Do...

Page 275: ...written in the modulus register or it can be a free running down counter 17 1 2 Block Diagram Figure 17 1 PIT Block Diagram 17 1 3 Low Power Mode Operation This subsection describes the operation of t...

Page 276: ...t PIT operation When debug mode is exited the PIT continues to operate in its pre debug mode state but any updates made in debug mode remain 17 2 Memory Map Register Definition This section contains a...

Page 277: ...eserved must be cleared 11 8 PRE Prescaler The read write prescaler bits select the internal bus clock divisor to generate the PIT clock To accurately predict the timing of the next count change the P...

Page 278: ...rom 0 to 1 during debug mode stops the PIT timer 4 OVW Overwrite Enables writing to PMRn to immediately overwrite the value in the PIT counter 0 Value in PMRn replaces value in PIT counter when count...

Page 279: ...PCSRn PIE bit is set the PIF flag issues an interrupt request to the CPU When the PCSRn OVW bit is set counter can be directly initialized by writing to PMRn without having to wait for the count to re...

Page 280: ...When the PCSRn OVW bit is set counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000 Figure 17 6 Counter in Free Running Mode 17 3 3 Timeout Specif...

Page 281: ...Integrated Microcontroller Reference Manual Rev 3 Freescale Semiconductor 17 7 The PIF flag is set when the PIT counter reaches 0x0000 The PIE bit enables the PIF flag to generate interrupt requests...

Page 282: ...Programmable Interrupt Timers PIT0 PIT1 MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 17 8 Freescale Semiconductor...

Page 283: ...e which can generate output waveforms and timer software delays These functions allow simultaneous input waveform measurements and output waveform generation Additionally channel 3 can be configured a...

Page 284: ...6 Bit Counter Interrupt Logic TOF TOI C0F C1F Edge Detect PT1 LOGIC Edge Detect CxF Channel 2 Channel3 GPTC3H GPTC3L 16 Bit Comparator 16 Bit Latch C3F PT3 LOGIC Edge Detect IOS0 IOS1 IOS3 OM OL0 TOV0...

Page 285: ...nal properties 18 5 1 GPT 2 0 The GPT 2 0 pins are for channel 2 0 input capture and output compare functions These pins are available for general purpose input output I O when not configured for time...

Page 286: ...ster GPTOC3D 8 R W 0x00 18 6 4 18 7 0x1A_0004 GPT Counter Register High GPTCNTH 2 8 R 0x00 18 6 5 18 7 0x1A_0005 GPT Counter Register Low GPTCNTL 2 8 R 0x00 18 6 5 18 7 0x1A_0006 GPT System Control Re...

Page 287: ..._001E GPT Port Data Direction Register GPTDDR 8 R W 0x00 18 6 19 18 16 1 Addresses not assigned to a register and undefined register bits are reserved for expansion 2 This register is 16 bits wide and...

Page 288: ...ervisor read write 7 6 5 4 3 2 1 0 R 0 0 0 0 FOC W Reset 0 0 0 0 0 0 0 0 Figure 18 3 GPT Input Compare Force Register GPCFORC Table 18 5 GPTCFORC Field Descriptions Field Description 7 4 Reserved shou...

Page 289: ...e pin is configured for output compare IOSx 1 The OC3Mn bits do not change the state of the PORTTnDDR bits These bits are read anytime write anytime 1 Corresponding PORTTn pin configured as output 0 N...

Page 290: ...6 5 4 3 2 1 0 R GPTEN 0 TFFCA 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 18 7 GPT System Control Register 1 GPTSCR1 Table 18 9 GPTSCR1 Field Descriptions Field Description 7 GPTEN Enables the general purp...

Page 291: ...rved should be cleared 3 0 TOV Toggles the output compare pin on overflow for each channel This feature only takes effect when in output compare mode When set it takes precedence over forced output co...

Page 292: ...nnel 3 shares a pin with the pulse accumulator input pin To use the PAI input clear the OM3 and OL3 bits and clear the OC3M3 bit in the output compare 3 mask register IPSBAR Offset 0x1A_000B GPTCTL2 A...

Page 293: ...Control Register 2 GPTSCR2 Table 18 14 GPTSCR2 Field Descriptions Field Description 7 TOI Enables timer overflow interrupt requests 1 Overflow interrupt requests enabled 0 Overflow interrupt requests...

Page 294: ...cess Supervisor read write 7 6 5 4 3 2 1 0 R 0 0 0 0 CF W Reset 0 0 0 0 0 0 0 0 Figure 18 14 GPT Flag Register 1 GPTFLG1 Table 18 15 GPTFLG1 Field Descriptions Field Description 7 4 Reserved should be...

Page 295: ...ld be cleared IPSBAR Offsets 0x1A_0010 GPTC0 0x1A_0012 GPTC1 0x1A_0014 GPTC2 0x1A_0016 GPTC3 Access Supervisor read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 296: ...nput enables divide by 64 clock to pulse accumulator and trailing falling edge on PAI sets PAIF flag Note The timer prescaler generates the divide by 64 clock If the timer is not active there is no di...

Page 297: ...d at the PAI pin In event counter mode the event edge sets PAIF In gated time accumulation mode the trailing edge of the gate signal at the PAI pin sets PAIF If the PAI bit in GPTPACTL is also set PAI...

Page 298: ...red and drives the pins only when they are configured as general purpose outputs Reading an input DDR bit 0 reads the pin state reading an output DDR bit 1 reads the latched value Writing to a pin con...

Page 299: ...ter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin An output compare on channel n sets the CnF flag The CnI bit enables the C...

Page 300: ...t logic by clearing the channel 3 output mode and output level bits OM3 and OL3 Also clear the channel 3 output compare 3 mask bit OC3M3 The PA counter register GPTPACNT reflects the number of active...

Page 301: ...ns as input capture or output compare pins The PORTTn data direction register controls the data direction of an input capture pin External pin conditions trigger input captures on input capture pins c...

Page 302: ...ut GPT disabled by GPTEN 0 1 0 0 IC 0 IC disabled X 0 In Ext Digital input Input capture disabled by EDGn setting 1 1 0 0 X 0 Out Data reg Digital output Input capture disabled by EDGn setting 1 0 0 0...

Page 303: ...16 bit pulse accumulator rolls over from 0xFFFF to 0x0000 If the PAOVI bit in GPTPACTL is also set PAOVF generates an interrupt request Clear PAOVF by writing a 1 to this flag NOTE When the fast flag...

Page 304: ...OTE When the fast flag clear all enable bit GPTSCR1 TFFCA is set any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG 18 9 4 Timer Overflow TOF TOF is set when the GP...

Page 305: ...odules DTIM0 DTIM1 DTIM2 or DTIM3 19 1 1 Overview Each DMA timer module has a separate register set for configuration and control The timers can be configured to operate from the internal bus clock or...

Page 306: ...and restart modes Programmable interrupt or DMA request on input capture or reference compare 19 2 Memory Map Register Definition The timer module registers shown in Table 19 1 can be modified at any...

Page 307: ...0x0442 0x0482 0x04C2 DMA Timer n Extended Mode Register DTXMRn 8 R W 0x00 19 2 2 19 4 0x0403 0x0443 0x0483 0x04C3 DMA Timer n Event Register DTERn 8 R W 0x00 19 2 3 19 5 0x0404 0x0444 0x0484 0x04C4 D...

Page 308: ...nterrupt if equals 0 0 Disable DMA request or interrupt for reference reached does not affect DMA request or interrupt on capture function 1 Enable DMA request or interrupt upon reaching the reference...

Page 309: ...erate a DMA request processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal Table 19 3 DTXMRn Field Descriptions Field Description 7 DMAEN DMA re...

Page 310: ...reference event The counter value DTCNn equals the reference value DTRRn Writing a 1 to REF clears the event condition Writing a 0 has no effect 0 CAP Capture event The counter value has been latched...

Page 311: ...divided by 16 or DTnIN IPSBAR Offset 0x0404 DTRR0 0x0444 DTRR1 0x0484 DTRR2 0x04C4 DTRR3 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Page 312: ...DMAEN are set a DMA request is asserted If DTERn CAP is set and DTXMRn DMAEN is cleared an interrupt is asserted 19 3 3 Reference Compare Each DMA timer can be configured to count up to a reference v...

Page 313: ...when the timer capture mode is selected or indeterminate operation results The 8 bit DTMRn PS prescaler value is set Using DTMRn RST counter is cleared and started Timer events are managed with an in...

Page 314: ...register setting TMR0 RST T0_LOOP move b TER0 D1 load TER0 and see if btst 1 D1 TER0 REF has been set beq T0_LOOP addi l 1 D2 Increment D2 cmp l 5 D2 Did D2 reach 5 i e timer ref has timed beq T0_FINI...

Page 315: ...M organization The chapter concludes with the programming model and a timing diagram 20 1 1 Block Diagram Figure 20 1 illustrates the QSPI module Figure 20 1 QSPI Block Diagram Queue Control Block Que...

Page 316: ...ons for details on which chip selects are pinned out Baud rates from 129 4 Kbps to 16 6 Mbps at 66 MHz internal bus frequency Programmable delays before and after transfers Programmable QSPI clock pha...

Page 317: ...al Name Hi Z or Actively Driven Function QSPI Data Output QSPI_DOUT Configurable Serial data output from QSPI QSPI Data Input QSPI_DIN N A Serial data input to QSPI Serial Clock QSPI_CLK Actively driv...

Page 318: ...Clock polarity Defines the clock polarity of QSPI_CLK 0 The inactive state value of QSPI_CLK is logic level 0 1 The inactive state value of QSPI_CLK is logic level 1 8 CPHA Clock phase Defines the QSP...

Page 319: ...nsfers in master mode by executing commands in the command RAM Automatically cleared by the QSPI when a transfer completes The user can also clear this bit to abort transfer unless QIR ABRTL is set Th...

Page 320: ...and continue execution 13 WRTO Wraparound location Determines where the QSPI wraps to in wraparound mode 0 Wrap to RAM entry zero 1 Wrap to RAM entry pointed to by QWR NEWQP 12 CSIV QSPI_CS inactive l...

Page 321: ...in an access error 13 Reserved should be cleared 12 ABRTL Abort lock out When set QDLYR SPE cannot be cleared by writing to the QDLYR QDLYR SPE is only cleared by the QSPI when a transfer completes 11...

Page 322: ...es external peripherals for transfer The command field provides transfer operations IPSBAR Offset 0x00_0350 QAR Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 ADDR...

Page 323: ...To keep the chip selects asserted for transfers beyond 16 words the QWR CSIV bit must be set to control the level that the chip selects return to after the first transfer 14 BITSE Bits per transfer en...

Page 324: ...NDQP points to the final command in the queue The internal pointer is initialized to the same value as QWR NEWQP During normal operation the following sequence repeats 1 The command pointed to by the...

Page 325: ...undefined immediately after a reset The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data 16 words of receive...

Page 326: ...ts of 16 bytes each divided into two fields The peripheral chip select field controls the QSPI_CS signal levels for the transfer The command control field provides transfer options A maximum of 16 com...

Page 327: ...equals zero the standard delay of one half the QSPI_CLK period is used The command RAM delay after transmit enable bit QCR DT enables the programmable delay period from the negation of the QSPI_CS sig...

Page 328: ...AM is loaded into the data serializer and transmitted Data that is simultaneously received is stored at the pointer address in receive RAM When the proper number of bits has been transferred the QSPI...

Page 329: ...25 MHz The QSPI RAM is set up for a queue of 16 transfers All four QSPI_CS signals are used in this example 1 Write the QMR with 0xB308 to set up 12 bit data words with the data shifted on the falling...

Page 330: ...Queued Serial Peripheral Interface QSPI MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 20 16 Freescale Semiconductor...

Page 331: ...external UART clock As Figure 21 1 shows each UART module interfaces directly to the CPU and consists of Serial communication channel Programmable clock generation Interrupt control logic and DMA requ...

Page 332: ...ured to enable the peripheral function of the appropriate pins refer to prior to configuring the UART module 21 1 2 Features The device contains three independent UART modules with Each clocked by an...

Page 333: ...iled description of each register and its specific function Flowcharts in Section 21 5 Initialization Application Information describe basic UART module programming Writing control bytes into the appr...

Page 334: ...T Command Registers UCRn 8 W 0x00 21 3 5 21 9 0x00_020C 0x00_024C 0x00_028C UART Receive Buffers URBn 8 R 0xFF 21 3 6 21 11 UART Transmit Buffers UTBn 8 W 0x00 21 3 7 21 12 0x00_0210 0x00_0250 0x00_02...

Page 335: ...verrun If the receiver and transmitter are incorrectly programmed for UnRTSn control UnRTSn control is disabled for both Transmitter RTS control is configured in UMR2n TXRTS 0 The receiver has no effe...

Page 336: ...11 1 0 B C Bits per character Selects the number of data bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits IPSBAR Offset...

Page 337: ...TS are set TXCTS controls the operation of the transmitter 0 UnCTS has no effect on the transmitter 1 Enables clear to send operation The transmitter checks the state of UnCTS each time it is ready to...

Page 338: ...orce parity the corresponding character in the FIFO was received with incorrect parity If UMR1n PM equals 11 multidrop PE stores the received address or data A D bit PE is valid only when RXRDYequals...

Page 339: ...he FIFO is not full but may hold up to two unread characters 1 A character was received and the receiver FIFO is now full Any characters received when the FIFO is full are lost 0 RXRDY Receiver ready...

Page 340: ...own state use this command instead of RECEIVER DISABLE when reconfiguring the receiver 011 RESET TRANSMITTER Immediately disables the transmitter and clears USRn TXEMP TXRDY No other registers are alt...

Page 341: ...re set If the transmitter is already enabled this command has no effect 10 TRANSMITTER DISABLE Terminates transmitter operation and clears USRn TXEMP TXRDY If a character is being sent when the transm...

Page 342: ...the transmit buffer when the UART s TXRDY equals 0 and the transmitter is disabled have no effect on the transmit buffer Figure 21 9 shows UTBn TB contains the character in the transmit buffer 21 3 8...

Page 343: ...the CPU last read UIPCRn Reading UIPCRn clears UISRn COS 1 A change of state longer than 25 50 s occurred on the UnCTS input UACRn can be programmed to generate an interrupt to the CPU when a change...

Page 344: ...DB Delta break 0 No new break change condition to report Section 21 3 5 UART Command Registers UCRn describes the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or end of...

Page 345: ...T transmitter or receiver are enabled UBG1n and UBG2n are write only and cannot be read by the CPU 21 3 12 UART Input Port Register UIPn The UIPn registers shown in Figure 21 15 show the current state...

Page 346: ...ernal bus clock is used so the user must enable the 16 bit divider Table 21 11 UIPn Field Descriptions Field Description 7 1 Reserved 0 CTS Current state of clear to send The UnCTS value is latched an...

Page 347: ...tions describe how to calculate baud rates 21 4 1 2 1 Internal Bus Clock Baud Rates When the internal bus clock is the UART clocking source it goes through a divide by 32 prescaler and then passes thr...

Page 348: ...e transmitter receives a disable command it continues until any character in the transmitter shift register is completely sent If the transmitter is reset through a software command operation stops im...

Page 349: ...e receiver detects a high to low mark to space transition of the start bit on UnRXD the state of UnRXD is sampled eight times on the edge of the bit time clock starting one half clock after the transi...

Page 350: ...ire character including the stop bit a character of all 0s loads into the receiver holding register and USRn RB RXRDY are set UnRXD must return to a high condition for at least one half bit time befor...

Page 351: ...SRn for the character at the top of the FIFO In block mode the USRn shows a logical OR of all characters reaching the top of the FIFO since the last RESET ERROR STATUS command Status is updated as cha...

Page 352: ...on UnTXD The receiver must be enabled but the transmitter need not be Figure 21 21 Automatic Echo Because the transmitter is inactive USRn TXEMP TXRDY is inactive and data is sent as it is received R...

Page 353: ...te in a wake up mode for multidrop or multiprocessor applications In this mode a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave sta...

Page 354: ...the received A D bit is 0 data tag If the receiver is enabled all received characters are transferred to the CPU through the receiver holding register during read operations In either case data bits l...

Page 355: ...checks When called SINIT places the UART in local loop back mode and checks for the following errors Transmitter never ready Receiver never ready Parity error Incorrect character received I O driver r...

Page 356: ...UART programming model to determine the end of transmission status Similarly the receive DMA request signal is asserted when the FIFO full or receive ready FFULL RXRDY flag in the interrupt status reg...

Page 357: ...ACR and appropriate PACR registers located in the SCM for DMA access to IPSBAR space 4 Initialize the DMA channel The DMA should be configured for cycle steal mode and a source and destination size of...

Page 358: ...f preferred program operation of clear to send TXCTS bit Select stop bit length SBx bits UCRn Enable transmitter and or receiver Figure 21 25 UART Mode Programming Flowchart Sheet 1 of 5 Table 21 15 U...

Page 359: ...Programming Flowchart Sheet 2 of 5 CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK Is Transmitter Ready Y N SNDCHR RxCHK Send Character To Transmitter Has C...

Page 360: ...e 21 25 UART Mode Programming Flowchart Sheet 3 of 5 A B B FRCHK Have Framing Error Set Framing Error Flag PRCHK Have Parity Error Set Parity Error Flag Get Character From Receiver Same As Transmitted...

Page 361: ...5 Was IRQ Caused By Beginning Of A Break SIRQ ABRKI N Clear Change in Break Status Bit ABRKI1 N Has End of break IRQ Arrived Yet Y Y Clear Change in Break Status Bit Remove Break Character From Receiv...

Page 362: ...13 ColdFire Integrated Microcontroller Reference Manual Rev 3 21 32 Freescale Semiconductor Figure 21 25 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH Is Transmitter Ready N Y Send Character To T...

Page 363: ...rates up to a maximum of the internal bus clock divided by 20 with reduced bus loading The maximum communication length and the number of devices connected are limited by a maximum bus capacitance of...

Page 364: ...I2C module has the following key features Compatibility with I2C bus standard version 2 1 Support for 3 3 V tolerant devices Multiple master operation Software programmable for one of 50 different ser...

Page 365: ...sent on the bus during the address transfer when the module is performing a master transfer Table 22 1 I2C Module Memory Map IPSBAR Offset Register Access Reset Value Section Page 0x00_0300 I2 C Addr...

Page 366: ...al to the internal bus clock divided by the divider shown below Due to potentially slow I2C_SCL and I2C_SDA rise and fall times bus signals are sampled at the prescaler frequency IC Divider IC Divider...

Page 367: ...ect 6 IIEN I2 C interrupt enable 0 I2 C module interrupts are disabled but currently pending interrupt condition is not cleared 1 I2C module interrupts are enabled An I2C interrupt occurs if I2SR IIF...

Page 368: ...data transmit cycle I2C_SDA sampled low when the master drives high during the acknowledge bit of a data receive cycle A start cycle is attempted when the bus is busy A repeated start cycle is request...

Page 369: ...nding a START signal see A in Figure 22 7 A START signal is defined as a high to low transition of I2C_SDA while I2C_SCL is high This signal denotes the beginning of a data transfer each data transfer...

Page 370: ...asis in the direction specified by the R W bit sent by the calling master Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high as Figure 22 7 shows I2C_SCL is pu...

Page 371: ...he slave The slave releases I2C_SDA for the master to generate a STOP or START signal Figure 22 9 22 3 5 STOP Signal The master can terminate communication by generating a STOP signal to free the bus...

Page 372: ...same slave in a different mode without releasing the bus The master transmits data to the slave first and then the master reads data from slave by reversing the R W bit Figure 22 11 Data Transfer Com...

Page 373: ...ces with shorter low periods enter a high wait state during this time see Figure 22 12 When all devices concerned have counted off their low period the synchronized clock I2C_SCL line is released and...

Page 374: ...ystem bus clock See Section 22 2 2 I2 C Frequency Divider Register I2FDR 2 Update the I2ADR to define its slave address 3 Set I2CR IEN to enable the I2 C bus interface system 4 Modify the I2CR to sele...

Page 375: ...the IIF bit if the interrupt function is disabled Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost When an interrupt occurs at the end of the ad...

Page 376: ...ime IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred interrupts resulting from subsequent data transfers have IAAS cleared A data transfer can...

Page 377: ...h to Rx Mode Dummy Read from I2DR Generate STOP Signal Read Data from I2DR And Store Set TXAK 1 Generate STOP Signal 2nd Last Byte to be Last Byte to be Arbitration Lost Clear IAL IAAS 1 IAAS 1 SRW 1...

Page 378: ...I2 C Interface MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 22 16 Freescale Semiconductor...

Page 379: ...sing simultaneous mode Ability to simultaneously sample and hold 2 inputs Ability to sequentially scan and store up to 8 measurements Internal multiplex to select two of 8 inputs Power savings modes a...

Page 380: ...Register 1 CTRL1 16 R W 0x5005 23 4 1 23 3 0x19_0002 Control Register 2 CTRL2 16 R W 0x0002 23 4 2 23 5 0x19_0004 Zero Crossing Control Register ADZCC 16 R W 0x0000 23 4 3 23 8 0x19_0006 Channel List...

Page 381: ...0 1 0 0 0 0 0 0 0 0 0 1 0 1 Figure 23 2 Control 1 Register CTRL1 Table 23 2 CTRL1 Field Descriptions Field Description 15 Reserved should be cleared 14 STOP0 Stop Conversion 0 bit When STOP0 is set th...

Page 382: ...interrupt to be generated upon completion of the scan For looping scan modes the interrupt triggers after the completion of each iteration of the loop 0 Interrupt disabled 1 Interrupt enabled 10 ZCIE...

Page 383: ...equential 011 Loop parallel 100 Triggered sequential 101 Triggered parallel default 110 Reserved do not use 111 Reserved do not use IPSBAR Offset 0x19_0002 CTRL2 Access read write 15 14 13 12 11 10 9...

Page 384: ...alue of DIV for several configurations IPSBAR Offset 0x19_0002 CTRL2 Access read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 STOP1 SYNC1 EOSIE1 0 0 0 0 0 SIMU LT DIV W START1 Reset 0 1 0 1 0 0 0 0...

Page 385: ...C0 input are used to start and stop scans in both converters simultaneously A scan ends in both converters when either converter encounters a disabled sample slot When the parallel scan completes the...

Page 386: ...odes the sample slots are converted in order from SAMPLE0 to SAMPLE7 Analog input pins can be sampled in any order including sampling the same input pin more than once In parallel modes converter A pr...

Page 387: ...12 11 10 9 8 7 6 5 4 3 2 1 0 R SAMPLE3 SAMPLE2 SAMPLE1 SAMPLE0 W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Figure 23 6 Channel List 1 Register ADLST1 Table 23 7 ADLST1 Field Descriptions Field Description...

Page 388: ...ved should be cleared 14 12 SAMPLE7 Sample input channel select 7 The settings for this field are given in Table 23 9 11 Reserved should be cleared 10 8 SAMPLE6 Sample input channel select 6 The setti...

Page 389: ...They are not cleared automatically on the next scan sequence IPSBAR Offset 0x19_000A ADSDIS Access read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 W...

Page 390: ...end of scan IRQ pending 11 EOSI0 End of Scan Interrupt 0 bit This bit indicates whether a scan of analog inputs has been completed since the last read of ADSTAT or a reset The EOSI0 bit is cleared by...

Page 391: ...d from the corresponding ADC results ADRSLTn register If polling the RDYn bits to determine if a particular sample is executed care should be taken not to start a new scan until all enabled samples ar...

Page 392: ...on of the value written is used This value is modified as shown in Figure 23 23 and the result of the subtraction is stored The SEXT bit is only set as a result of this subtraction and is not directly...

Page 393: ...DHLMTn correspond to result registers ADRSLTn The high limit register is used for the comparison of result high limit The low limit register is used for the comparison of result low limit Limit checki...

Page 394: ...w Limit Registers ADLLMTn Table 23 15 ADLLMTn Field Descriptions Field Description 15 Reserved should be cleared 14 3 LLMT Low limit 2 0 Reserved should be cleared IPSBAR Offset 0x19_0032 ADHLMT0 0x19...

Page 395: ...efined The voltage reference generator and at least one converter must be powered up to use the ADC module 2 Manual power down controls Each converter and the voltage reference generator have a manual...

Page 396: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ASB 0 0 PSTS2 PSTS1 PSTS0 PUDELAY APD PD2 PD1 PD0 W Reset 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 Figure 23 16 Power Control Register POWER Table 23 18 POWER Field Des...

Page 397: ...efer to the Device Data Sheet for further details 3 APD Auto Power Down Mode bit Auto power down mode disables converters when they are not in use for a scan APD takes precedence over ASB When a scan...

Page 398: ...onverter A bit This bit forces Converter A to power down Setting PD0 powers down converter A immediately The results of a scan using converter A is invalid when PD0 is set When PD0 is cleared converte...

Page 399: ...rter A and in order SAMPLE4 7 by converter B in parallel scan SAMPLE slots may be disabled using the SDIS register The following pairs of analog inputs can be configured as a differential pair AN0 1 A...

Page 400: ...part of SDIS register DS0 DS3 for A DS4 DS7 for B Figure 23 19 Parallel Mode Operation of the ADC The ADC can be configured to perform a single scan and halt perform a scan when triggered or perform...

Page 401: ...directed to ADRSLT0 3 and any of AN4 AN7 can be directed to ADRSLT4 7 4 MUXing for parallel mode differential conversions During any conversion cycle sample either member of differential pair AN0 1 or...

Page 402: ...middle switch is closed providing the differential channel to the differential input of the A D Table 23 20 Analog MUX Controls for Each Conversion Mode continued Conversion Mode Channel Select Switc...

Page 403: ...it to the plus terminal of the A D core The minus terminal of the A D core is connected to the VREFL reference during this mode The ADC measures the voltage of the selected analog input and compares i...

Page 404: ...n the max value 32760 4095 8 when the plus input is VREFH and the minus input is VREFL return 0 when the plus input is at VREFL and the minus input is at VREFL and scale linearly between based on the...

Page 405: ...unsigned and equals the cyclic converter unsigned result The range of the result registers ADRSLTn is 0x0000 0x7FF8 assuming the offset ADOFSn registers are set to zero The processor can write to the...

Page 406: ...NCFG A differential measurement is made if a SAMPLE slot refers to either member of a differential pair Refer to the CHNCFG field description in the CTRL1 register for details of differential and sing...

Page 407: ...he A and B converter start and stop independently according to their own controls They may be simultaneous phase shifted or asynchronous depending on when scans are initiated on the respective convert...

Page 408: ...8 sample slots defined by the ADLST1 and ADLST2 registers A scan is the process of stepping through these sample slots converting the analog input indicated by that slot and storing the result Slots...

Page 409: ...y on the first conversion Loop parallel Upon an initial start or enabled sync pulse converter A captures Samples 0 3 and converter B captures Samples 4 7 Each time a converter completes its current sc...

Page 410: ...lock is enabled ADC 1 in the SIM module s SIM_PCE register In this mode the ADC uses the conversion clock as the ADC clock source when active or idle To minimize conversion latency it is recommended t...

Page 411: ...d at the start of all scans allowing the ADC to stabilize when switching to normal current mode from a completely powered off condition This mode uses less power than normal and more power than auto s...

Page 412: ...d at the start of the scan In auto power down mode when the ADC goes from idle to active a converter is only powered up if it is required for the scan as determined by the ADLST1 ADLST2 and SDIS regis...

Page 413: ...r management is set to normal It is also active during all ADC power up for a period of time determined by the PUDELAY field in the power POWER register After the power up delay times out the ADC cloc...

Page 414: ...NCn signals As shown in Figure 23 27 the first scan started is re synchronized to the system clock but the second scan may wait up to 5 additional system clocks before starting Also which converter is...

Page 415: ...urrent Figure 23 28 ADC Voltage Reference Circuit When tying VREFH to the same potential as VDDA relative measurements are being made with respect to the amplitude of VDDA It is imperative that specia...

Page 416: ...ure 23 28 illustrates the internal workings of the ADC voltage reference circuit VREFH must be noise filtered a minimum configuration is shown in the figure 23 5 11 Supply Pins VDDA and VSSA Dedicated...

Page 417: ...s a synchronous series of pulses having programmable period and duty cycle With a suitable low pass filter the PWM can be used as a digital to analog converter Figure 24 1 PWM Block Diagram Internal B...

Page 418: ...able 24 1 PWM Memory Map IPSBAR Offset1 2 1 Addresses not assigned to a register and undefined register bits are reserved for expansion Write accesses to these reserved address spaces and reserved reg...

Page 419: ...0 0 0 0 0 0 Figure 24 2 PWM Enable Register PWME Table 24 2 PWME Field Descriptions Field Description 7 PWME5 PWM channel 7 output enable If enabled the PWM signal becomes available at PWMOUT7 when i...

Page 420: ...an occur during the transition IPSBAR Offset 0x1B_0001 PWMPOL Access User Read Write 7 6 5 4 3 2 1 0 R PPOL7 0 PPOL5 0 PPOL3 0 PPOL1 0 W Reset 0 0 0 0 0 0 0 0 Figure 24 3 PWM Polarity Register PWMPOL...

Page 421: ...SCLA for more information on how the different clock rates are generated The even numbered channels clock select has no effect when the corresponding PWMCTL CONn n 1 bit is set For example if PWMCTL C...

Page 422: ...tailed description of the concatenation function 3 Reserved should be cleared 2 0 PCKA Clock A prescaler select These three bits control the rate of Clock A which can be used for PWM channels 1 and 5...

Page 423: ...bled The channel 5 clock select polarity center align enable and enable bits control this concatenated output 5 CON23 Concatenates PWM channels 2 and 3 to form one 16 bit PWM channel 0 Channels 2 and...

Page 424: ...equation Eqn 24 2 Any value written to this register causes the scale counter to load the new scale value PWMSCLB IPSBAR Offset 0x1B_0008 PWMSCLA Access User Read Write 7 6 5 4 3 2 1 0 R SCALEA W Res...

Page 425: ...for center aligned mode the immediate load of duty and period registers with values from the buffers and the output to change according to the polarity bit The counter is also cleared at the end of t...

Page 426: ...associated PWM channel To calculate the output duty cycle high time as a percentage of period for a particular channel Eqn 24 4 Table 24 10 PWMCNTn Field Descriptions Field Description 7 0 COUNT Curre...

Page 427: ...PWMDTY4 0x1B_0021 PWMDTY5 0x1B_0022 PWMDTY6 0x1B_0023 PWMDTY7 Access User Read Write 7 6 5 4 3 2 1 0 R DUTY W Reset 1 1 1 1 1 1 1 1 Figure 24 12 PWM Duty Registers PWMDTYn Table 24 12 PWMDTYn Field De...

Page 428: ...ct 0 No change in PWM7IN input 1 Change in PWM7IN input 6 IE PWM interrupt enable An interrupt is triggered to the device s interrupt controller when PWMSDN IF is set 0 Interrupt is disabled 1 Interru...

Page 429: ...e input clock is also disabled when all PWM channels are disabled PWMEn 0 Clock A and B are scaled values of the input clock The value is software selectable for clock A and B and has options of 1 1 2...

Page 430: ...down counter to be re loaded Otherwise when changing rates the counter would have to count down to 0x01 before counting at the proper rate Forcing the associated counter to re load the scale register...

Page 431: ...When one of the bits in the PWMPOL register is set the associated PWM channel output is high at the beginning of the waveform then goes low when the duty count is reached Conversely if the polarity bi...

Page 432: ...be set to up the immediate load of duty and period registers with values from the buffers and the output to change according to the polarity bit When the channel is disabled PWMEn 0 the counter stops...

Page 433: ...4 3 2 3 The counter counts from 0 to the value in the period register minus 1 NOTE Changing the PWM output mode from left aligned to center aligned output or vice versa while channels are operating ca...

Page 434: ...WM counter decrements and reaches zero the counter direction changes from a down count back to an up count and a load from the double buffer period and duty registers to the associated registers is pe...

Page 435: ...els are disabled As shown in Figure 24 20 when channels 2 and 3 are concatenated channel 2 registers become the high order bytes of the double byte channel When channels 0 and 1 are concatenated chann...

Page 436: ...following table summarizes the boundary conditions for the PWM regardless of the output mode left or center aligned and 8 bit normal or 16 bit concatenation Table 24 15 16 bit Concatenation Mode Summa...

Page 437: ...r 24 21 Table 24 16 PWM Boundary Cases PWMDTYn PWMPERn PPOLn PWMn Output 0x00 indicates no duty 0x00 1 Always Low 0x00 indicates no duty 0x00 0 Always High XX 0x001 indicates no period 1 Counter 0x00...

Page 438: ...Pulse Width Modulation PWM Module MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 24 22 Freescale Semiconductor...

Page 439: ...t B The CAN protocol was primarily but not only designed to be used as a vehicle serial data bus meeting the specific requirements of this field real time processing reliable operation in the EMI envi...

Page 440: ...es the transmit drive waveshaping and receive compare functions required for communicating on the CAN bus It can also provide protection against damage to the FlexCAN caused by a defective CAN bus or...

Page 441: ...mber Time stamp based on 16 bit free running timer Global network time synchronized by a specific message Programmable I O modes Maskable interrupts Independent of the transmission medium an external...

Page 442: ...disabled during freeze mode it shuts down the system clocks sets the LPMACK bit and clears the FRZACK bit If the module is disabled during transmission or reception FlexCAN does the following Waits to...

Page 443: ...Out of the lower 128 bytes only part is occupied by various registers The upper 256 bytes are fully used for the message buffer structures as described in Section 25 3 9 Message Buffer Structure Table...

Page 444: ...0x1C_0000 CANMCR Access Supervisor read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R MDIS FRZ 0 HALT NOT RDY 0 SOFT RST FRZ ACK SUPV 0 0 LPM ACK 0 0 0 0 W Reset 1 1 0 1 1 0 0 0 1 0 0 1 0 0...

Page 445: ...d is automatically cleared when reset completes The user should poll this bit to know when the soft reset has completed 0 Soft reset cycle completed 1 Soft reset cycle initiated 24 FRZACK Freeze ackno...

Page 446: ...Prescaler division factor Defines the ratio between the clock source frequency set by CLK_SRC bit and the serial clock S clock frequency The S clock period defines the time quantum of the CAN protoco...

Page 447: ...ority rule is used 6 BOFFREC Bus off recovery mode Defines how FlexCAN recovers from bus off state If this bit is cleared automatic recovering from bus off state occurs according to the CAN Specificat...

Page 448: ...ser except for the fact that the data takes some time to be actually written to the register If desired software can poll the register to discover when the data was actually written 3 LOM Listen only...

Page 449: ...on the CAN bus This captured value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a message Table 25 5 Mask Examples for Normal Extended Messag...

Page 450: ...AN bus state transitions If the value of TXECTR or RXECTR increases to be greater than or equal to 128 the FLTCONF field in the error and status register ERRSTAT is updated to reflect error passive st...

Page 451: ...e greater than 127 it is not incremented further even if more errors are detected while being a receiver At the next successful message reception the counter is set to a value between 119 and 127 to r...

Page 452: ...transmit bit error 1 At least one bit sent as dominant was received as recessive 13 ACKERR Acknowledge error Indicates whether an acknowledgment has been correctly received for a transmitted message 0...

Page 453: ...affected by soft reset if the LOM bit is set 00 Error active 01 Error passive 1x Bus off 3 Reserved must be cleared 2 BOFFINT Bus off interrupt Used to request an interrupt when the FlexCAN enters the...

Page 454: ...age buffer MB0 to MB15 interrupt These bits allow the CPU to designate which buffers generate interrupts after successful transmission reception 0 The interrupt for the corresponding buffer is disable...

Page 455: ...s of the standard identifier 11 bits and the extended identifier 18 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 CODE SRR IDE RTR LENGTH TIME STAMP 0x...

Page 456: ...d it is considered as a successful bit transmission 0 Indicates the current MB has a data frame to be transmitted 1 Indicates the current MB has a remote frame to be transmitted 19 16 LENGTH Length of...

Page 457: ...rwritten into a full buffer 0010 If the code indicates OVERRUN but the CPU reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 0110 If the code al...

Page 458: ...x MB with a 1000 code is inactive refer to Table 25 13 An MB not programmed with 0000 or 1000 is temporarily deactivated does not participate in the current arbitration matching run when the CPU write...

Page 459: ...gement MBM that scans the entire MB memory looking for the highest priority message to be transmitted All MBs programmed as transmit buffers are scanned to find the lowest ID or the lowest MB number d...

Page 460: ...r 2 ID optional needed only if a mask was used 3 Data field words 4 Free running timer Releases internal lock optional Upon reading the control and status word if the BUSY bit is set in the CODE field...

Page 461: ...g ID is free to receive a new frame if the MB is not locked see Section 25 3 16 3 Locking and Releasing Message Buffers The CODE field is EMPTY FULL or OVERRUN but the CPU has already serviced the MB...

Page 462: ...st Suppose for example that two MBs have a matching ID to a received frame and the user deactivated the first matching MB after FlexCAN has scanned the second The received frame is lost even if the se...

Page 463: ...data frame automatically in response to a remote frame or to transmit a remote frame and then wait for the responding data frame to be received When transmitting a remote frame the user initializes a...

Page 464: ...low the user to configure the bit timing parameters The CANCTRL CLK_SRC bit defines whether the module uses the internal bus clock or the output of the crystal oscillator via the EXTAL pin The crystal...

Page 465: ...ngs and the related parameter values NOTE It is the user s responsibility to ensure the bit time settings are in compliance with the CAN standard For bit time calculations use an IPT Information Proce...

Page 466: ...ode should be exited and the clocks resumed before applying soft reset The clock source CANCTRL CLK_SRC should be selected while the module is in disable mode After the clock source is selected and th...

Page 467: ...b Set the required mask bits in the IMASK register for all message buffer interrupts and the CANCTRL for bus off and error interrupts 5 Clear the CANMCR HALT bit At this point the FlexCAN attempts to...

Page 468: ...FlexCAN MCF5213 ColdFire Integrated Microcontroller Reference Manual Rev 3 25 30 Freescale Semiconductor...

Page 469: ...omplex In BDM processor complex is halted and a variety of commands can be sent to the processor to access memory registers and peripherals The external emulator uses a three pin serial full duplex ch...

Page 470: ...ot affect hardware breakpoint logic Added BDM address attribute register BAAR BKPT configurable interrupt CSR BKD Level 1 and level 2 triggers on OR condition in addition to AND SYNC_PC command to dis...

Page 471: ...ising edge appears in the center of valid PST and DDATA output PSTCLK indicates when the development system should sample PST and DDATA values The following figure shows PSTCLK timing with respect to...

Page 472: ...some opcodes a branch target address may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed indicated by the PST marker value preceding the DD...

Page 473: ...or clock cycles 1 Use PST 0x5 to identify that a taken branch is executed 2 Using the PST pins optionally signal the target address to be displayed sequentially on the DDATA pins Encodings 0x9 0xB ide...

Page 474: ...reated as 32 bit quantities regardless of the number of implemented bits These registers are also accessed through the BDM port by the commands WDMREG and RDMREG described in Section 26 5 3 3 Command...

Page 475: ...shared function For example if an operand address breakpoint is loaded into the debug module a BDM command to access memory overwrites an address breakpoint in ABHR If a data breakpoint is configured...

Page 476: ...ware breakpoint trigger If TRG is set a hardware breakpoint halted the processor core and forced entry into BDM Reset the debug GO command or reading CSR from the BDM port only clear TRG 25 HALT Proce...

Page 477: ...dress See Section 26 3 1 Begin Execution of Taken Branch PST 0x5 7 Reserved must be cleared 6 NPL Non pipelined mode Determines whether the core operates in pipelined mode or not 0 Pipelined mode 1 No...

Page 478: ...ger The register value is compared with address attribute signals from the processor s local high speed bus as defined by the setting of the trigger definition register TDR AATR is accessible in super...

Page 479: ...s Field Description 15 RM Read write mask Setting RM masks R in address comparisons 14 13 SZM Size mask Setting an SZM bit masks the corresponding SZ bit in address comparisons 12 11 TTM Transfer type...

Page 480: ...4 3 TT Transfer type Compared with the local bus transfer type signals 00 Normal processor access 01 Reserved 10 Emulator mode access 11 Acknowledge CPU space access These bits also define the TT enco...

Page 481: ...2EBL Enable level 2 breakpoint Global enable for the breakpoint trigger 0 Disables all level 2 breakpoints 1 Enables all level 2 breakpoint triggers 28 22 L2ED Enable level 2 data breakpoint Setting a...

Page 482: ...ion Address_range Data_condition 1 Level 2 trigger PC_condition Address_range Data_condition Note Debug Rev A only had the AND condition available for the triggers 14 L1T Level 1 trigger Determines th...

Page 483: ...a value other than the DBR contents 0 No inversion 1 Invert data breakpoint comparators 4 2 L1EA Enable level 1 address breakpoint Setting an L1EA bit enables the corresponding address breakpoint Clea...

Page 484: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Address Reset Figure 26 7 PC Breakpoint Register PBR0 Table 26 10 PBR0 Field Descriptions Field Description 31 0 Addre...

Page 485: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Mask Reset Figure 26 9 PC Breakpoint Mask Register PBMR Table 26 12 PBMR Field Descriptions Field Description 31...

Page 486: ...write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Data Reset Figure 26 11 Data Breakpoint Registers DBR Table 26 15 DBR Field Descriptions Field Des...

Page 487: ...r flash programming Provides absolute control of the processor and thus the system This feature allows quick hardware debugging with the same tool set used for firmware development 26 5 1 CPU Halt Alt...

Page 488: ...pecifically if the PC register was loaded the GO command causes the processor to exit halted state and pass control to the instruction address in the PC bypassing normal reset exception processing If...

Page 489: ...t be used to indicate the start of a serial transfer The development system must count clock cycles in a given transfer C0 C4 are described as C0 Set the state of the DSI bit C1 First synchronization...

Page 490: ...ated messages listed below The not ready response can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor clock p...

Page 491: ...840 word 0x1880 lword Dump memory block DUMP Used with READ to dump large blocks of memory An initial READ executes to set up the starting address of the block and to retrieve the first result A DUMP...

Page 492: ...s data or operand data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 26 16 BDM Command Format Table 26 21 BDM Field Descriptions Field Descript...

Page 493: ...e illegal command encoding If this occurs the development system should retransmit the command NOTE A not ready response can be ignored except during a memory referencing cycle Otherwise the debug mod...

Page 494: ...mpleted commands S equals 1 for illegal commands not ready responses and transfers with bus errors Section 26 5 2 BDM Serial Interface describes the receive packet format Freescale reserves unassigned...

Page 495: ...ta register The data is supplied most significant word first Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete 26 5 3 3 3 Read Mem...

Page 496: ...ndefined 0x0001 S equals 1 is returned if a bus error occurs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0x9 0x0 0x0 A 31 16 A 15 0 Result X X X X X X X X D 7 0 Word Command 0x1 0x9 0x4 0x0...

Page 497: ...fines address space Hardware forces low order address bits to 0s for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Forma...

Page 498: ...mmand to access large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the first DUMP...

Page 499: ...g the operand size to be dynamically altered Command Result Formats Command Sequence Figure 26 27 DUMP Command Sequence Operand Data None 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0xD 0x0...

Page 500: ...s in a temporary register after the memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the temporary reg...

Page 501: ...ormal instruction execution resumes Prefetching begins at the current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while the pr...

Page 502: ...he processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of the CSR BTB bits The specific sequence of PST and DDATA values is defin...

Page 503: ...emory control registers are always 32 bits wide regardless of register width The second and third words of the command form a 32 bit address which the debug module uses to generate a special bus cycle...

Page 504: ...quely identify one as the SSP and the other as the USP Rather the hardware uses one 32 bit register as the currently active A7 the other is named the OTHER_A7 Therefore the contents of the two hardwar...

Page 505: ...tion for the Rc encoding and for additional notes on writes to the A7 stack pointers and the EMAC programming model Command Result Formats Command Sequence Figure 26 39 WCREG Command Sequence Operand...

Page 506: ...uence Operand Data None Result Data The contents of the selected debug register are returned as a longword value The data is returned most significant word first 26 5 3 3 14 Write Debug Module Registe...

Page 507: ...on The debug module provides four types of breakpoints PC with mask PC without mask operand address range and data with mask These breakpoints can be configured into one or two level triggers with the...

Page 508: ...a sample point which occurs once per instruction Again the hardware forces the PC breakpoint to occur before the targeted instruction executes and is precise This is possible because the PC breakpoint...

Page 509: ...s the processor in emulation mode when debug interrupt exception processing begins Setting CSR TRC forces the processor into emulation mode when trace exception processing begins While operating in em...

Page 510: ...words 26 7 Processor Status Debug Data Definition This section specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instruction...

Page 511: ...ination bchg b l Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l data ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD dest...

Page 512: ...x8 DD destination move l ea y ea x PST 0x1 PST 0xB DD source PST 0xB DD destination move w ea y ea x PST 0x1 PST 0x9 DD source PST 0x9 DD destination move w CCR Dx PST 0x1 move w Dy data CCR PST 0x1 m...

Page 513: ...PST 0xB DD source PST 0xB DD destination suba l ea y Ax PST 0x1 PST 0xB DD source operand subi l data Dx PST 0x1 subq l data ea x PST 0x1 PST 0xB DD source PST 0xB DD destination subx l Dy Dx PST 0x1...

Page 514: ...the taken branch indicator 0x5 2 For JMP and JSR instructions the optional target instruction address is displayed only for those effective address fields defining variant addressing modes This includ...

Page 515: ...me the ColdFire processor is in the given mode 26 8 Freescale Recommended BDM Pinout The ColdFire BDM connector is a 26 pin Berg connector arranged 2 x 13 as shown below msac w Ry Rx PST 0x1 msac w Ry...

Page 516: ...BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved1 GND GND RESET EVDD2 GND Freescale reserved GND IVDD BKPT DSCLK Developer reserved1 DSI DSO GND F...

Page 517: ...ta and chip control pins from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST 27 1 1 Block Diagram Figure 27 1 shows the block diagram of the JT...

Page 518: ...TAG_EN 1 Background debug mode BDM for more information refer to Section 26 5 Background Debug Mode BDM JTAG_EN 0 27 2 External Signal Description The JTAG module has five input and one output externa...

Page 519: ...tion 27 2 3 Test Mode Select Breakpoint TMS BKPT The TMS pin is the test mode select input that sequences the TAP state machine TMS is sampled on the rising edge of TCLK The TMS pin has an internal pu...

Page 520: ...3 Memory Map Register Definition The JTAG module registers are not memory mapped and are only accessible through the TDO DSO pin All registers described below are shift in and parallel load 27 3 1 Ins...

Page 521: ...alue to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update DR state IR 4 0 0_0001 IDCODE Access User read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 522: ...signals 27 4 Functional Description 27 4 1 JTAG Module The JTAG module consists of a TAP controller state machine which is responsible for generating all control signals that execute the JTAG instruc...

Page 523: ...T 0000 Selects boundary scan register while applying fixed values to output pins and asserting functional reset IDCODE 0001 Selects IDCODE register for shift SAMPLE PRELOAD 0010 Selects boundary scan...

Page 524: ...shifting it through the boundary scan register to the TDO output by using the shift DR state Both the data capture and the shift operation are transparent to system operation NOTE External synchroniza...

Page 525: ...he TDI and TDO pin When the user transitions the TAP controller to the UPDATE_DR state the register transfers its value to a parallel hold register It allows the control chip to test functions indepen...

Page 526: ...Restrictions The test logic is a static logic design and TCLK can be stopped in a high or low state without loss of data However the system clock is not synchronized to TCLK internally Any mixed oper...

Page 527: ...es and Table A 3 is a detailed memory map including all of the registers for on chip modules Table A 1 CPU Space Register Memory Map Address Name Mnemonic Size CPU 0x800 Other Stack Pointer OTHER_A7 3...

Page 528: ..._02C0 Reserved 64 bytes IPSBAR 0x00_0300 I2C 64 bytes IPSBAR 0x00_0340 QSPI 64 bytes IPSBAR 0x00_0380 Reserved 128 bytes IPSBAR 0x00_0400 DMA Timer 0 64 bytes IPSBAR 0x00_0440 DMA Timer 1 64 bytes IPS...

Page 529: ...x0013 Core Watchdog Service Register CWSR 8 IPSBAR 0x0014 DMA Request Control Register DMAREQC 32 IPSBAR 0x0018 Peripheral Power Management Register Low PPMRL 32 IPSBAR 0x001C Default Bus Master Park...

Page 530: ...DCR2 32 IPSBAR 0x0130 Source Address Register 3 SAR3 32 IPSBAR 0x0134 Destination Address Register 3 DAR3 32 IPSBAR 0x0138 Byte Count Register 3 DMA Status Register 3 BCR3 DSR3 32 IPSBAR 0x013C DMA C...

Page 531: ...0x0250 Read UART Input Port Change Register 1 UIPCR1 8 Write UART Auxiliary Control Register 11 UACR1 8 IPSBAR 0x0254 Read UART Interrupt Status Register 1 UISR1 8 Write UART Interrupt Mask Register...

Page 532: ...d Reserved 8 Write UART Output Port Bit Set Command Register 2 UOP12 8 IPSBAR 0x02BC Read Reserved 8 Write UART Output Port Bit Reset Command Register 2 UIP02 8 I2 C Registers IPSBAR 0x0300 I2 C Addre...

Page 533: ...r 2 DTRR2 32 IPSBAR 0x0488 DMA Timer Capture Register 2 DTCR2 32 IPSBAR 0x048C DMA Timer Counter Register 2 DTCN2 32 IPSBAR 0x04C0 DMA Timer Mode Register 3 DTMR3 16 IPSBAR 0x04C2 DMA Timer Extended M...

Page 534: ...x0C50 Interrupt Control Register 0 16 ICR016 8 IPSBAR 0x0C51 Interrupt Control Register 0 17 ICR017 8 IPSBAR 0x0C52 Interrupt Control Register 0 18 ICR018 8 IPSBAR 0x0C53 Interrupt Control Register 0...

Page 535: ...rol Register 0 49 ICR049 8 IPSBAR 0x0C72 Interrupt Control Register 0 50 ICR050 8 IPSBAR 0x0C73 Interrupt Control Register 0 51 ICR051 8 IPSBAR 0x0C74 Interrupt Control Register 0 52 ICR052 8 IPSBAR 0...

Page 536: ...0x0FF8 Global Level 6 Interrupt Acknowledge Register GL6IACK 8 IPSBAR 0x0FFC Global Level 6 Interrupt Acknowledge Register GL7IACK 8 GPIO Registers IPSBAR 0x10_0000 Reserved 8 IPSBAR 0x10_0001 Reserv...

Page 537: ...0_0020 Reserved 8 IPSBAR 0x10_0021 Port QS Data Direction Register DDRQS 8 IPSBAR 0x10_0022 Port TA Data Direction Register DDRTA 8 IPSBAR 0x10_0023 Port TC Data Direction Register DDRTC 8 IPSBAR 0x10...

Page 538: ...PORTUBP SETUB 8 IPSBAR 0x10_003B Port UC Pin Data Set Data Register PORTUCP SETUC 8 IPSBAR 0x10_003C Reserved 8 IPSBAR 0x10_003D Reserved 8 IPSBAR 0x10_003E Reserved 8 IPSBAR 0x10_003F Reserved 8 IPSB...

Page 539: ...Port TC Pin Assignment Register PTCPAR 8 IPSBAR 0x10_0058 Port TD Pin Assignment Register PTDPAR 8 IPSBAR 0x10_0059 Port UA Pin Assignment Register PUAPAR 8 IPSBAR 0x10_005A Port UB Pin Assignment Re...

Page 540: ...SBAR 0x11_0007 Low Power Control Register LPCR 8 IPSBAR 0x11_0008 Reset Configuration Register RCON 16 IPSBAR 0x11_000A Chip Identification Register CIR 16 Clock Module Registers IPSBAR 0x12_0000 Synt...

Page 541: ...6 IPSBAR 0x19_0006 Channel List Register 1 ADLST1 16 IPSBAR 0x19_0008 Channel List Register 2 ADLST2 16 IPSBAR 0x19_000A Sample Disable Register ADSDIS 16 IPSBAR 0x19_000C Status Register ADSTAT 16 IP...

Page 542: ...Flag Register GPTPAFLG 8 IPSBAR 0x1A_001A Pulse Accumulator Counter Register GPTPACNT 16 IPSBAR 0x1A_001D GPT Port Data Register GPTPORT 8 IPSBAR 0x1A_001E GPT Port Data Direction Register GPTDDR 8 Pu...

Page 543: ...PWMDTY1 8 IPSBAR 0x1B_001E PWM Channel Duty Register 2 PWMDTY2 8 IPSBAR 0x1B_001F PWM Channel Duty Register 3 PWMDTY3 8 IPSBAR 0x1B_0020 PWM Channel Duty Register 4 PWMDTY4 8 IPSBAR 0x1B_0021 PWM Cha...

Page 544: ...ecurity Register CFMSEC 32 IPSBAR 0x1D_0010 CFM Protection Register CFMPROT 32 IPSBAR 0x1D_0014 CFM Supervisor Access Register CFMSACC 32 IPSBAR 0x1D_0018 CFM Data Access Register CFMDACC 32 IPSBAR 0x...

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