Freescale Semiconductor ColdFire MCF5211, Reference Manual

Page: 182 / 544

General Purpose I/O Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
11-6 Freescale Semiconductor
Setting any bit in a DDR n register configures the corresponding port n pin as an output. Clearing any bit
in a DDR n register configures the corresponding pin as an input.
IPSBAR
Offsets:
0x10_001D (DDRDD)
0x10_001E (DDRAN) Access: User read/write
7 6 5 4 3 2 1 0
R
DDR n 7 DDR n 6 DDR n 5 DDR n 4 DDR n 3 DDR n 2 DDR n 1 DDR n 0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-7. Port Data Direction Registers with Bits 7:0 Implemented (DDRDD, DDRAN)
IPSBAR
Offsets:
0x10_0022 (DDRTA)
0x10_0023 (DDRTC)
0x10_0024 (DDRTD)
0x10_0025 (DDRUA)
0x10_0026 (DDRUB)
0x10_0027 (DDRUC) Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0
DDR n 3 DDR n 2 DDR n 1 DDR n 0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-8. Port Data Direction Registers with Bits 3:0 Implemented (DDRTA, DDRTC, DDRTD, DDRUA,
DDRUB, DDRUC)
IPSBAR
Offset: 0x10_0021 (DDRQS)
Access: User read/write
7 6 5 4 3 2 1 0
R 0
DDR n 6 DDR n 5 DDR n 4 DDR n 3 DDR n 2 DDR n 1 DDR n 0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-9. Port QS Data Direction Register (DDRQS)
IPSBAR
Offset: 0x10_001C (DDRNQ)
Access: User read/write
7 6 5 4 3 2 1 0
R
DDR n 7 DDR n 6 DDR n 5 DDR n 4 DDR n 3 DDR n 2 DDR n 1
0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-10. Port NQ Data Direction Register (DDRNQ)