MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
3-1
Chapter 3
ColdFire Core
This section describes the organization of the Version 2 (V2) ColdFire
®
processor core and an overview
of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the
ColdFire Family Programmer’s Reference Manual
.
3.1
Processor Pipelines
Figure 3-1. V2 ColdFire Core Pipelines
As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
instruction, fetches the required operands, and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
Instruction
Instruction
FIFO
Decode & Select,
Address
IAG
IC
IB
DSOC
AGEX
Instruction Buffer
Address
Generation
Fetch Cycle
Generation,
Execute
Operand Fetch
Data [31:0]
Instruction
Operand
Pipeline
Execution
Fetch
Pipeline
Address [31:0]
