Freescale Semiconductor ColdFire MCF5211, Reference Manual

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System Control Module (SCM)
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 10-15
IPSBAR
Offset:
Offset (PACR n ) Access: read/write
7 6 5 4 3 2 1 0
R
LOCK1 ACCESS_CTRL1 LOCK0 ACCESS_CTRL0
W
Reset: 0 0 0 0 0 0 0 0
Figure 10-9. Peripheral Access Control Register (PACR n )
Table 10-10. PACR Field Descriptions
Field Description
7
LOCK1
This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR
generates an error termination and the contents of the register are not affected. Only a system reset clears
this flag.
6–4
ACCESS_CTRL1
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in
Table 10-11 .
3
LOCK0
This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to the PACR
generates an error termination and the contents of the register are not affected. Only a system reset clears
this flag.
2–0
ACCESS_CTRL0
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in
Table 10-11 .
Table 10-11. PACR ACCESSCTRL Bit Encodings
Bits Supervisor Mode User Mode
000 Read/Write No Access
001 Read No Access
010 Read Read
011 Read No Access
100 Read/Write Read/Write
101 Read/Write Read
110 Read/Write Read/Write
111 No Access No Access
Table 10-12. Peripheral Access Control Registers (PACRs)
IPSBAR Offset Name
Modules Controlled
1
ACCESS_CTRL1 ACCESS_CTRL0
0x024 PACR0 SCM —
0x025 PACR1 — DMA
0x026 PACR2 UART0 UART1