MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
22-1
Chapter 22
I
2
C Interface
22.1
Introduction
This chapter describes the I
2
C module, clock synchronization, and I
2
C programming model registers. It
also provides extensive programming examples.
22.1.1
Overview
I
2
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications that require
occasional communication between many devices over a short distance. The flexible I
2
C bus allows
additional devices to connect to the bus for expansion and system development.
The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of
operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus
loading. The maximum communication length and the number of devices connected are limited by a
maximum bus capacitance of 400 pF.
The I
2
C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data
corruption in the event that multiple devices attempt to control the bus simultaneously. This feature
supports complex applications with multiprocessor control and can be used for rapid testing and alignment
of end products through external connections to an assembly-line computer.
NOTE
The I
2
C module is compatible with the Philips I
2
C bus protocol. For
information on system configuration, protocol, and restrictions, see
The I
2
C
Bus Specification, Version 2.1
.
NOTE
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to
Chapter 11, “General Purpose I/O Module”
)
prior to configuring the I
2
C module.
is a block diagram of the I
2
C module.
