FlexCAN
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
25-29
2. Initialize message buffers.
a) The control/status word of all message buffers must be written as an active or inactive message
buffer.
b) All other entries in each message buffer should be initialized as required.
3. Initialize RXGMASK, RX14MASK, and RX15MASK registers for acceptance mask as needed.
4. Initialize FlexCAN interrupt handler.
a) Initialize the interrupt controller registers for any needed interrupts. See
for more information.
b) Set the required mask bits in the IMASK register (for all message buffer interrupts) and the
CANCTRL (for bus off and error interrupts).
5. Clear the CANMCR[HALT] bit. At this point, the FlexCAN attempts to synchronize with the CAN
bus.
25.4.1
Interrupts
There are three interrupt sources for the FlexCAN module. A combined interrupt for all 16 MBs is
generated by combining all the interrupt sources from MBs. This interrupt gets generated when any of the
16 MB interrupt sources generates a interrupt. In this case, the CPU must read the IFLAG register to
determine which MB caused the interrupt. The other two interrupt sources (bus off and error) act in the
same way, and are located in the ERRSTAT register. The bus off and error interrupt mask bits are located
in the CANCTRL register.
