IEEE 1149.1 Test Access Port (JTAG)
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
27-8
Freescale Semiconductor
27.4.3.1
IDCODE Instruction
The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the
TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and
other part identification data. The shift register lsb is forced to logic 1 on the rising edge of TCLK
following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the
IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising
edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a
TAP reset, the IDCODE register is selected automatically.
27.4.3.2
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
•
SAMPLE - obtain a sample of the system data and control signals present at the MCU input pins
and before the boundary scan cell at the output pins. This sampling occurs on the rising edge of
TCLK in the capture-DR state when the IR contains the $2 opcode. The sampled data is accessible
by shifting it through the boundary scan register to the TDO output by using the shift-DR state.
Both the data capture and the shift operation are transparent to system operation.
NOTE
External synchronization is required to achieve meaningful results because
there is no internal synchronization between TCLK and the system clock.
•
PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or
CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in
initialization data. The update-DR state and the falling edge of TCLK can then transfer this data to
TEST_LEAKAGE
1,2
0101
Selects bypass register while tri-stating all output pins and assert to high the
jtag_leakage signal
ENABLE_TEST_CTRL
0110
Selects TEST_CTRL register
HIGHZ
1001
Selects bypass register while tri-stating all output pins and asserting
functional reset
LOCKOUT_RECOVERY
1011
Allows for the erase of the TFM flash when the part is secure
CLAMP
1100
Selects bypass while applying fixed values to output pins and asserting
functional reset
BYPASS
1111
Selects bypass register for data operations
Reserved
all others
3
Decoded to select bypass register
1
Instruction for manufacturing purposes only
2
TRST pin assertion or power-on reset is required to exit this instruction.
3
Freescale reserves the right to change the decoding of the unused opcodes in the future.
Table 27-5. JTAG Instructions (continued)
Instruction
IR[3:0]
Instruction Summary
