Freescale Semiconductor ColdFire MCF5211, Reference Manual

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Interrupt Controller Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 12-11
12.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPR n )
Each time an IACK is performed, the interrupt controller responds with the vector number of the highest
priority source within the level being acknowledged. In addition to providing the vector number directly
for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level
and priority being acknowledged. This register provides the association between the acknowledged
physical interrupt request number and the programmed interrupt level/priority. The contents of this
read-only register are described in
Figure 12-8 and Table 12-10 .
12.3.6 Interrupt Control Registers (ICR nx )
Each ICR nx , where x = 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level (0–7).
As shown in Table 12-11 , all ICR nx registers can be read, but only ICR n 8 through ICR n 63 can be written.
Registers ICR n 1 through ICR n 7 are read-only because the interrupt levels for IRQ1 through IRQ7 are
hard-coded (see Section 12.1.1, “Interrupt Controller Theory of Operation” ). The registers are described
in Figure 12-9 and Table 12-12 .
It is the responsibility of the software to program the ICR nx registers with unique and non-overlapping
level and priority definitions. Failure to program the ICR nx registers in this manner can result in undefined
behavior. If a specific interrupt request is completely unused, the ICR nx value can remain in its reset (and
disabled) state.
IPSBAR
Offset: 0x0C19 (IACKLPR n )
Access: Read-only
7 6 5 4 3 2 1 0
R 0 LEVEL PRI
W
Reset: 0 0 0 0 0 0 0 0
Figure 12-8. IACK Level and Priority Register (IACKLPR n )
Table 12-10. IACKLPR n Field Descriptions
Field Description
7 Reserved
6–4
LEVEL
Interrupt level. Represents the interrupt level currently being acknowledged.
3–0
PRI Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only