DMA Controller Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
14-15
If BWC equals 000, the request signal remains asserted until BCR
n
reaches zero. DMA has priority over
the core. In this scheme, the arbiter can always force the DMA to relinquish the bus. See
“Bus Master Park Register (MPARK).”
14.4.5
Termination
An unsuccessful transfer can terminate for one of the following reasons:
•
Error conditions—When the DMA encounters a read or write cycle that terminates with an error
condition, DSR
n
[BES] is set for a read and DSR
n
[BED] is set for a write before the transfer is
halted. If the error occurred in a write cycle, data in the internal holding register is lost.
•
Interrupts—If DCR
n
[INT] is set, the DMA drives the appropriate internal interrupt signal. The
processor can read DSR
n
to determine whether the transfer terminated successfully or with an
error. DSR
n
[DONE] is then written with a one to clear the interrupt and the DONE and error bits.
14.5
Document Revision History
