System Control Module (SCM)
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
10-7
10.5.4
Core Watchdog Control Register (CWCR)
The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no
controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE]. It is disabled
by default. If enabled, the watchdog timer requires the periodic execution of a core watchdog servicing
sequence. If this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer
interrupt or a hardware reset, as programmed, by CWCR[CWRI]. If the timer times out and the core
watchdog transfer acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted.
If a core watchdog timer interrupt acknowledge cycle has not occurred after another timeout, CWT TA is
asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus cycle.
The setting of CWCR[CWTAVAL] indicates that the watchdog timer TA was asserted.
When the core watchdog timer times out and CWCR[CWRI] is programmed for a software reset, an
internal reset is asserted and CRSR[CWDR] is set. To prevent the core watchdog timer from interrupting
or resetting, the CWSR must be serviced by performing the following sequence:
1. Write 0x55 to CWSR.
2. Write 0xAA to the CWSR.
Both writes must occur in order before the time-out, but any number of instructions can be executed
between the two writes. This order allows interrupts and exceptions to occur, if necessary, between the two
writes. Caution should be exercised when changing CWCR values after the software watchdog timer has
been enabled with the setting of CWCR[CWE], because it is difficult to determine the state of the core
watchdog timer while it is running. The countdown value is constantly compared with the time-out period
specified by CWCR[CWT]. The following steps must be taken to change CWT:
1. Disable the core watchdog timer by clearing CWCR[CWE].
2. Reset the counter by writing 0x55 and then 0xAA to CWSR.
3. Update CWCR[CWT].
4. Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed in step 3.
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer
acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At
system reset, the software watchdog timer is disabled.
IPSBAR
Offset: 0x0011 (CWCR)
Access: read/write
7
6
5
4
3
2
1
0
R
CWE
CWRI
CWT[2:0]
CWTA
CWTAVAL
CWTIF
W
Reset:
0
0
0
0
0
0
0
0
Figure 10-4. Core Watchdog Control Register (CWCR)
