Freescale Semiconductor ColdFire MCF5211, Reference Manual

Page: 199 / 544

Interrupt Controller Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 12-7
12.3.2 Interrupt Mask Register (IMRH n , IMRL n )
The IMRH n and IMRL n registers are each 32 bits and provide a bit map for each interrupt to allow the
request to be disabled (1 = disable the request, 0 = enable the request). The IMR n is set to all ones by reset,
disabling all interrupt requests. The IMR n can be read and written. A write that sets bit 0 of the IMR forces
the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability.
IPSBAR
Offset: 0x0C04 (IPRL n )
Access: Read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R INT[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R INT[15:1] 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-2. Interrupt Pending Register Low (IPRL n )
Table 12-4. IPRL n Field Descriptions
Field Description
31–1
INT
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRL n bit determines whether an
interrupt condition can generate an interrupt. At every system clock, the IPRL n samples the signal generated by the
interrupting source. The corresponding IPRL n bit reflects the state of the interrupt signal even if the corresponding
IMRL n bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
0 Reserved, should be cleared.
IPSBAR
Offset: 0x0C08 (IMRH n )
Access: Read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
INT_MASK[63:48]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INT_MASK[47:32]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 12-3. Interrupt Mask Register High (IMRH n )