Force Computers SYS68K/CPU-40, User Manual

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS
3-60
3.9.1 Address Map of the PI/T1 Registers
PI/T1 is accessible via the 8 bit local I/O bus (byte mode). The following table shows the register layout
of the PI/T1.
Table 3-14: PI/T1 Register Layout
Default I/O Base Address: $FF80 0000
Default Offset: $0000 0C00
Default Name: PI_T1
Address Offset Reset
HEX HEX Value
Label Description
FF800C00 00 00 PIT1 PGCR Port General Control Register
FF800C01 01 00 PIT1 PSRR Port Service Request Register
FF800C02 02 00 PIT1 PADDR Port A Data Direction Register
FF800C03 03 00 PIT1 PBDDR Port B Data Direction Register
FF800C04 04 00 PIT1 PCDDR Port C Data Direction Register
FF800C05 05 00 PIT1 PIVR Port Interrupt Vector Register
FF800C06 06 00 PIT1 PACR Port A Control Register
FF800C07 07 00 PIT1 PBCR Port B Control Register
FF800C08 08 -- PIT1 PADR Port A Data Register
FF800C09 09 -- PIT1 PBDR Port B Data Register
FF800C0A 0A -- PIT1 PAAR Port A Alternate Register
FF800C0B 0B -- PIT1 PBAR Port B Alternate Register
FF800C0C 0C -- PIT1 PCDR Port C Data Register
FF800C0D 0D -- PIT1 PSR Port Status Register
FF800C10 10 00 PIT1 TCR Timer Control Register
FF800C11 11 0F PIT1 TIVR Timer Interrupt Vector Register
FF800C12 12 -- PIT1 CPR Counter Preload Register
FF800C13 13 -- " "
FF800C14 14 -- " "
FF800C15 15 -- " "
FF800C16 16 -- PIT1 CNTR Count Register
FF800C17 17 -- " "
FF800C18 18 -- " "
FF800C19 19 -- " "
FF800C1A 1A 00 PIT1 TSR Timer Status Register