SECTION 3
HARDWARE USER'S MANUAL
6-27
6.8 RESET Generation
There is an IEEE 1014 compatible SYSRESET* driver installed on the CPU board. The RESET generator
circuitry is operable if the power supply VCC is at least 3 volts. The RESET signal can be asserted (low)
on any one of the following conditions:
!
Front Panel RESET switch toggled
!
Voltage Sensor detects VCC below limit (4.8V)
!
Execution of the RESET instruction by the microprocessor on the board
The asserted RESET signal will be held low for at least 200 milliseconds after removing all the above
conditions.
When the Reset Switch is toggled twice a Powerup equivalent Reset can be generated. The time lapse
immediately after the Reset Switch is released must be 0,2 seconds or less.
6.8.1 The Front Panel RESET Switch
The upper switch on the front panel of the CPU board is the RESET switch. Toggling it provides a reset
of all on-board devices, independent from the jumper options. With the jumper B13 3-6 connection
inserted, the SYSRESET* signal of the VMEbus backplane will be asserted. When the RUN LED is red,
the processor is in the HALT state. For example, this state will be entered if a double bus fault occurs. A
reset of the board must be performed by toggling the RESET switch or by asserting the SYSRESET*
backplane signal. The light of the RUN LED is also red while the RESET generator drives the reset. After
reset, the red light must change to green.
6.8.2 The Voltage Sensor Module FH001
The voltage sensor module FH001 is included with the RESET generator. Power up reset is provided by
this sensor, as soon as the supply voltage VCC has reached 3 volts. RESET will be asserted if VCC is less
than 4.8 volts on the board, once the jumper B2 pin 1-2 is removed (B). This jumper is removed upon
delivery. When the jumper at B2 1-2 is inserted (A), RESET will be asserted if VCC is less than 4.6 volts.
RESET will stay asserted at least 200 milliseconds after the supply voltage has passed the threshold.
Jumperfield B2 pin 1-2 must be removed for normal operation, and may be inserted for test purposes.
Figure 6-7: Jumper Settings for Jumperfield B2
+))))))),
+))))))),
A) B2 1
*
o
)))
o
*
2 B) B2 1
*
o o
*
2
4.6V
.)))))))-
4.8V
.)))))))-
(default)
Summary of Contents for SYS68K/CPU-40
Page 2: ...INTRODUCTION...
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Page 8: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 Figure 1 1 Photo of the CPU Board...
Page 9: ...SECTION 1 INTRODUCTION 1 3 Figure 1 2 Block Diagram of the CPU Board...
Page 34: ...SECTION 1 INTRODUCTION 2 21 Figure 2 2 The Front Panel of the CPU Board...
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Page 42: ...INSTALLATION...
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Page 57: ...HARDWARE USER S MANUAL...
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Page 83: ...SECTION 3 HARDWARE USER S MANUAL 3 13 Figure 3 2 Location Diagram of the System EPROM Area...
Page 92: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 22 3 5 6 Location Diagram of Jumperfield B16...
Page 141: ...SECTION 3 HARDWARE USER S MANUAL 3 71 Figure 3 25 Location Diagram of Header B12...
Page 152: ...SECTION 3 HARDWARE USER S MANUAL 4 3 Figure 4 1 Front Panel of the CPU Board...
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Page 172: ...SECTION 3 HARDWARE USER S MANUAL 6 17 Figure 6 2 Location Diagram of Jumperfield B19...
Page 179: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 24 Figure 6 4 Location Diagram of B13...
Page 187: ...APPENDIX TO THE HARDWARE USER S MANUAL...
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Page 207: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 3 E 1 Circuit Schematics of DRM 01...
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Page 209: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 5 E 2 Circuit Schematics of SRM 01...
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Page 213: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL F 3 Location Diagram for All Jumperfields...
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Page 228: ...COPIES OF DATA SHEETS...
Page 229: ...COPIES OF DATA SHEETS RTC 72423 DUSCC 68562 PI T 68230...
Page 230: ...USERS NOTES...
Page 231: ...USERS NOTES...
Page 232: ...USERS NOTES...
Page 233: ...OPTIONS APPLICATIONS MODIFICATIONS...
Page 234: ...INTRODUCTION TO VMEPROM IN USE WITH THE SYS68K CPU 40 41...
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Page 268: ...APPENDIX TO THE INTRODUCTION TO VMEPROM...
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Page 319: ...THE APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE...