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SECTION 3
HARDWARE USER'S MANUAL
3-1
3. THE LOCAL BUS
3.1 The FGA-002 Gate Array
The FGA-002 Gate Array featured on this CPU board has 24,000 gates and 281 pins.
The FGA-002 Gate Array controls the local bus and builds the interface to the VMEbus. It also includes
a DMA controller, complete interrupt management, a message broadcast interface (FMB), timer functions,
and mailbox locations.
This gate array monitors the local bus. This in turn signifies that if any local device is to be accessed, the
gate array takes charge of all control signals in addition to used address and data signals.
The FGA-002 Gate Array serves as a manager for the VMEbus. All VMEbus address and data lines are
connected to the gate array through the buffers. Additional functions such as the VMEbus interrupt handler
are also installed on the FGA-002 Gate Array. The SGL VMEbus arbiter in the FGA/002 must remain
disabled because the 4 level VME arbiter of the CPU board is designed in a separate device and connected
with the VME bus (please refer to chapter 6.4
VMEbus Arbitration for further information).
The start address of the FGA-002 Gate Array registers is $FFD00000. All registers of the gate array and
associated functions are described in detail in the FGA-002 Gate Array User's Manual.
Summary of Contents for SYS68K/CPU-40
Page 2: ...INTRODUCTION...
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Page 8: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 Figure 1 1 Photo of the CPU Board...
Page 9: ...SECTION 1 INTRODUCTION 1 3 Figure 1 2 Block Diagram of the CPU Board...
Page 34: ...SECTION 1 INTRODUCTION 2 21 Figure 2 2 The Front Panel of the CPU Board...
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Page 42: ...INSTALLATION...
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Page 57: ...HARDWARE USER S MANUAL...
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Page 83: ...SECTION 3 HARDWARE USER S MANUAL 3 13 Figure 3 2 Location Diagram of the System EPROM Area...
Page 92: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 22 3 5 6 Location Diagram of Jumperfield B16...
Page 141: ...SECTION 3 HARDWARE USER S MANUAL 3 71 Figure 3 25 Location Diagram of Header B12...
Page 152: ...SECTION 3 HARDWARE USER S MANUAL 4 3 Figure 4 1 Front Panel of the CPU Board...
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Page 172: ...SECTION 3 HARDWARE USER S MANUAL 6 17 Figure 6 2 Location Diagram of Jumperfield B19...
Page 179: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 24 Figure 6 4 Location Diagram of B13...
Page 187: ...APPENDIX TO THE HARDWARE USER S MANUAL...
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Page 207: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 3 E 1 Circuit Schematics of DRM 01...
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Page 209: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 5 E 2 Circuit Schematics of SRM 01...
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Page 213: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL F 3 Location Diagram for All Jumperfields...
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Page 228: ...COPIES OF DATA SHEETS...
Page 229: ...COPIES OF DATA SHEETS RTC 72423 DUSCC 68562 PI T 68230...
Page 230: ...USERS NOTES...
Page 231: ...USERS NOTES...
Page 232: ...USERS NOTES...
Page 233: ...OPTIONS APPLICATIONS MODIFICATIONS...
Page 234: ...INTRODUCTION TO VMEPROM IN USE WITH THE SYS68K CPU 40 41...
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Page 268: ...APPENDIX TO THE INTRODUCTION TO VMEPROM...
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Page 319: ...THE APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE...