Force Computers SYS68K/CPU-40, User Manual

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS
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6.2 VMEbus Slave Interface
6.2.1 The Access Address
The onboard shared RAM of the CPU board is also accessible from the VMEbus side. Both the begin and
end address are programmable in 4 Kbyte increments inside the FGA-002. The complete address decoding
for the shared RAM logic is performed inside the FGA-002 Gate Array. For details on the programming of
the access address, please refer to the BOOT Software description in the FGA-002 User's Manual.
6.2.2 Data Transfer Size of the Shared RAM
The VMEbus interface of the shared RAM is 32 bits wide. It supports 32 bit, 16 bit, and 8 bit as well as
unaligned (UAT) and read-modify-write (RMW) transfers.
6.2.3 Address Modifier Decoding and A24 Slave Mode
For access to the shared RAM from the VMEbus side, extended (A32) and standard (A24) accesses are
allowed.
The FGA-002 only recognizes A32 accesses. The access address for an A32 access can be programmed
as described above.
If an A24 access takes place additional onboard hardware translates this A24 access to an A32 access to
the FGA-002. This means that the standard address modifier code from the VMEbus is modified to
extended address modifier to the FGA-002. In A24 mode the address lines A31 to A24 of the VMEbus must
not be used for address decoding. Therefore these address lines are driven to the FGA-002 via an
additional driver. The value of these address bits are programmable via the PI/T1 Port B. For detailed
information about the address map and register layout of the PI/T1 please refer to the chapter
Address Map
of the PI/T1 Registers.