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SECTION 1
INTRODUCTION
2-7
2.3 The System EPROM
The CPU board offers two 40-pin EPROM sockets for the installation of two 16-bit wide EPROM devices.
The EPROMs present a full 32-bit data path to the processor enabling maximum performance. The
following devices are supported in the system EPROM area:
Supported Device Types in the System EPROM Area:
Organization
Total Memory Capacity
64K x 16
256 Kbytes
128K x 16
512 Kbytes
256K x 16
1 Mbyte
512K x 16
2 Mbytes
2.4 The Local SRAM
The CPU board contains a 128K * 8 bit SRAM. Battery backup is provided via the on-board battery or the
5VSTDBY line.
2.5 The Local FLASH EPROM
A 128 Kbyte FLASH EPROM is included on the base board of the CPU-40 which can be used as additional
data backup under conditions of power down for long periods. FLASH EPROM is ideal to hold details of
the board status, such as software revision or user data which is to be kept permanently.
2.6 The Boot EPROM
The CPU board contains, in addition to the two system EPROMs, a single boot EPROM to boot the local
microprocessor, initialize all I/O devices and program the board-dependent functions of the FGA-002. All
basic initialization of the I/O devices and the FGA-002 are made through the boot EPROM.
In addition, the boot EPROM contains user utility routines, which may be called out of the user's application
program. These routines provide easy software access to the functionality of the FGA-002 (DMA controller,
FORCE Message Broadcast, Interrupt Management, etc.).
Summary of Contents for SYS68K/CPU-40
Page 2: ...INTRODUCTION...
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Page 8: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 Figure 1 1 Photo of the CPU Board...
Page 9: ...SECTION 1 INTRODUCTION 1 3 Figure 1 2 Block Diagram of the CPU Board...
Page 34: ...SECTION 1 INTRODUCTION 2 21 Figure 2 2 The Front Panel of the CPU Board...
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Page 42: ...INSTALLATION...
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Page 57: ...HARDWARE USER S MANUAL...
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Page 83: ...SECTION 3 HARDWARE USER S MANUAL 3 13 Figure 3 2 Location Diagram of the System EPROM Area...
Page 92: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 22 3 5 6 Location Diagram of Jumperfield B16...
Page 141: ...SECTION 3 HARDWARE USER S MANUAL 3 71 Figure 3 25 Location Diagram of Header B12...
Page 152: ...SECTION 3 HARDWARE USER S MANUAL 4 3 Figure 4 1 Front Panel of the CPU Board...
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Page 172: ...SECTION 3 HARDWARE USER S MANUAL 6 17 Figure 6 2 Location Diagram of Jumperfield B19...
Page 179: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 24 Figure 6 4 Location Diagram of B13...
Page 187: ...APPENDIX TO THE HARDWARE USER S MANUAL...
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Page 207: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 3 E 1 Circuit Schematics of DRM 01...
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Page 209: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 5 E 2 Circuit Schematics of SRM 01...
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Page 213: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL F 3 Location Diagram for All Jumperfields...
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Page 228: ...COPIES OF DATA SHEETS...
Page 229: ...COPIES OF DATA SHEETS RTC 72423 DUSCC 68562 PI T 68230...
Page 230: ...USERS NOTES...
Page 231: ...USERS NOTES...
Page 232: ...USERS NOTES...
Page 233: ...OPTIONS APPLICATIONS MODIFICATIONS...
Page 234: ...INTRODUCTION TO VMEPROM IN USE WITH THE SYS68K CPU 40 41...
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Page 268: ...APPENDIX TO THE INTRODUCTION TO VMEPROM...
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Page 319: ...THE APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE...