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SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

6-22

Table 6-14: Description of the IRQ Generation Register

Bit

Value

Mode

Description

0

--

--

No function

1

R/W

VMEbus interrupt IRQ1

1

Active

0

Inactive (automatically set to zero again)

2

R/W

VMEbus interrupt IRQ2

1

Active

0

Inactive (automatically set to zero again)

3

R/W

VMEbus interrupt IRQ3

1

Active

0

Inactive (automatically set to zero again)

4

R/W

VMEbus interrupt IRQ4

1

Active

0

Inactive (automatically set to zero again)

5

R/W

VMEbus interrupt IRQ5

1

Active

0

Inactive (automatically set to zero again)

6

R/W

VMEbus interrupt IRQ6

1

Active

0

Inactive (automatically set to zero again)

7

R/W

VMEbus interrupt IRQ7

1

Active

0

Inactive (automatically set to zero again)

6.5.2 The Interrupt Vector Register

The interrupt vector register holds the byte wide interrupt vector for the VMEbus interrupts. It can be read
and written and must be set to the right value before an interrupt is activated. It must not be changed as
long as a VMEbus Interrupt from the board is pending.

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Summary of Contents for SYS68K/CPU-40

Page 1: ...GmbH All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS SYS68K CPU 40 41 User s Man...

Page 2: ...INTRODUCTION...

Page 3: ...This page was intentionally left blank...

Page 4: ...2 6 The Boot EPROM 2 7 2 7 The FGA 002 2 8 2 8 The PI T 68230 2 9 2 8 1 The I O Configuration of PI T1 2 10 2 8 2 The I O Configuration of PI T2 2 10 2 9 The Real Time Clock 72423 2 11 2 10 The DUSCC...

Page 5: ...2 Figure 1 2 Block Diagram of the CPU Board 1 3 Figure 2 1 Location Diagram for All Jumperfields 2 20 Figure 2 2 The Front Panel of the CPU Board 2 21 LIST OF TABLES Table 1 1 The Memory Map 1 6 Tabl...

Page 6: ...iii This page was intentionally left blank...

Page 7: ...l real time operation and responsiveness The EAGLE modules are installed on the CPU board via the FLXi FORCE Local eXpansion interface This provides a full 32 bit interface between the base board and...

Page 8: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 Figure 1 1 Photo of the CPU Board...

Page 9: ...SECTION 1 INTRODUCTION 1 3 Figure 1 2 Block Diagram of the CPU Board...

Page 10: ...s installed in the FGA 002 Two system EPROM devices supporting 40 pin devices Access from the 68040 using a 32 bit data path One boot EPROM for local booting initialization of the I O chips and config...

Page 11: ...our level VMEbus arbiter SYSCLK driver VMEbus interrupter IR 1 7 VMEbus interrupt handler IH 1 7 Support for ACFAIL and SYSFAIL Bus timeout counters for local and VMEbus access 15 sec VMEPROM Real Tim...

Page 12: ...ses 8 Mbyte Shared Memory A32 D32 D24 D16 D8 01000000 F9FFFFFF VMEbus Addresses 16 Mbyte Shared Memory A32 D32 D24 D16 D8 FA000000 FAFFFFFF Message Broadcast Area FB000000 FBFEFFFF VMEbus A24 D32 D24...

Page 13: ...ief overview of the local I O devices and the equivalent base address Table 1 2 The Base Addresses of the Local I O Devices BASE ADDRESS DEVICE FF803000 RTC 72423 FF802000 DUSCC1 68562 FF802200 DUSCC2...

Page 14: ...struction and data cache Cache functionality is strengthened by the built in on chip bus snooping logic which instantly supports cache logic during multimaster applications Instruction administration...

Page 15: ...ion and 4 Kbyte data cache On chip paged memory management unit Pipelined architecture with parallelism allowing accesses to internal caches bus transfers and instruction execution in parallel Synchro...

Page 16: ...he access address for the VMEbus is programmable in 4 Kbyte steps through the FGA 002 The defined memory range can be write protected in coordination with the address modifier codes For example in sup...

Page 17: ...For example in supervisor mode the memory can be read and written in user mode memory can only be read The DRAM module includes byte parity check for local and VMEbus accesses If a parity error is de...

Page 18: ...protected in coordination with the address modifier codes For example in supervisor mode the memory can be read and written in user mode memory can only be read Parity check is not necessary for SRAM...

Page 19: ...can be write protected in coordination with the address modifier codes For example in supervisor mode the memory can be read and written in user mode memory can only be read Parity check is not necess...

Page 20: ...H EPROM is included on the base board of the CPU 40 which can be used as additional data backup under conditions of power down for long periods FLASH EPROM is ideal to hold details of the board status...

Page 21: ...Additional functions such as theVMEbus interrupt handler are also installed on the FGA 002 The on chip DMA controller can access the local memory VMEbus memory and on board devices which are able to...

Page 22: ...nal modes 8 or 16 bits wide The PI T timer contains a 24 bit wide counter and a 5 bit prescaler Features of the PI T MC68000 Bus Compatible Port Modes Include Bit I O Unidirectional 8 bit and 16 bit B...

Page 23: ...routed to a 24 pin header which allows the connection of a flat cable 8 bits are connected to port A of the PI T and can be used as inputs or outputs with the remaining 4 bits being connected to the h...

Page 24: ...egulation unnecessary and allows easy design Direct bus compatibility 120 ns access time Incorporated built in time hour minute second and date year month week day counters 12 hour and 24 hour clock s...

Page 25: ...d control circuits Features of the DUSCC Dual full duplex synchronous asynchronous receiver and transmitter Multiprotocol operation consisting of BOP HDLC ADCCP SDLC SDLC Loop X 25 or X 75 link level...

Page 26: ...election of the RS422 RS485 compatible interface The DUSCCcan interrupt the local CPU at a specified programmable IRQ level I O Signals for DUSCC1 The I O signal assignment of channel 1 to 2 is listed...

Page 27: ...DSR X X a29 Data Set Ready RTS X a30 Request to Send CTS X a31 Clear to Send GND a32 Signal GND NOTE This is only possible if these VMEbus P2 lines are not used by an EAGLE module I O Signals for DUS...

Page 28: ...des for A16 A24 and A32 addressing are fully supported in master mode In slave mode the address modifiers for A32 and A24 are fully supported Read Modify Write cycles are fully supported to allow mult...

Page 29: ...ard is able to access the VMEbus interface independently from the microprocessor enabling VMEbus communication to take place without impacting the processing capabilities of the rest of the board for...

Page 30: ...ch as breakpoints tracing memory display memory modify and host communication VMEPROM supports several memory and I O boards on the VMEbus to take full advantage of the file manager and kernel functio...

Page 31: ...Settings for System EPROMs and SRAM EEPROM Jumperfield Description Default Schematics Connection B11 System EPROM device select 1 6 SH5 A4 B16 FLASH EPROM write dis enable 1 2 SH4 C2 Default Jumper S...

Page 32: ...RESET 3 6 Drive VMEbus RESET 4 5 Default Jumper Settings for Test Jumperfield Description Default Schematics Connection B17 Clock Signal to CPU 1 2 SH16 A1 Headers for 12 Bit I O and 8 Bit I O Jumperf...

Page 33: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 2 20 Figure 2 1 Location Diagram for All Jumperfields...

Page 34: ...SECTION 1 INTRODUCTION 2 21 Figure 2 2 The Front Panel of the CPU Board...

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Page 36: ...Lines Real Time Clock with On board Battery Backup 72423 VMEbus Interface A32 A24 A16 D8 D16 D32 UAT RMW Master A32 A24 D8 D16 D32 RMW Slave Four Level Arbiter Yes SYSCLK Driver Yes Mailbox Interrupts...

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Page 38: ...FLXi VMEPROM Documentation included SYS68K CPU 40D 16 01 33 0 MHz 68040 based CPU board with DMA 16 Mbyte shared DRAM 4 serial I O channels EAGLE 01C SCSI floppy disk and Ethernet Interface VMEPROM Do...

Page 39: ...ables 9 pin micro D Sub male connector to 9 pin D Sub female connector length 2 m SYS68K CABLE MICRO 9 SET 2 Set of four adapter cables 9 pin micro D Sub male connector to 25 pin D Sub female connecto...

Page 40: ...ter 3 9 4 has been eliminated Chapter 3 9 12 New Board Identification Chapter 3 9 16 1 and 0 were switched AUG 23 1991 2 Rework for PCB Revision 2 FEB 03 1992 3 MAY 05 1992 Editorial changes throughou...

Page 41: ...ANUAL FORCE COMPUTERS 5 2 7 MAR 14 1996 Section 3 DRM 01 4 and DRM 01 16 have been replaced by DRM 03 and DRM 05 respectively Appendix F 2 The description of jumperfield B13 has been corrected 8 Edito...

Page 42: ...INSTALLATION...

Page 43: ...This page was intentionally left blank...

Page 44: ...n their lifetime Before installing or uninstalling the board read this Installation section Before installing or uninstalling the board in a VME rack Check all installed boards for steps that you have...

Page 45: ...This page was intentionally left blank...

Page 46: ...n of the Terminal 1 3 1 4 The Default Hardware Setup 1 4 2 INSTALLATION IN THE RACK 2 1 2 1 Power ON 2 1 2 2 Correct Operation 2 2 3 ENVIRONMENTAL REQUIREMENTS 3 1 LIST OF FIGURES Figure 1 1 Front Pan...

Page 47: ...ii This page was intentionally left blank...

Page 48: ...ifferent functions of the rotary switches are described in detail in the Introduction to VMEPROM as well as in the Hardware User s Manual of this particular CPU board 1 2 The Function Switch Positions...

Page 49: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 Figure 1 1 Front Panel of CPU Board and the Rotary Switch Positions...

Page 50: ...on the front panel Signal Input Output Required 9 Pin Micro Description 9 Pin D Sub of the D Sub Adapter Cable Connector DCD X 1 Data Carrier Detect 1 RXD X X 2 Receive Data 2 TXD X X 3 Transmit Data...

Page 51: ...Female Connectors 5 4 3 2 1 9 8 7 6 GND DTR TXD RXD DCD GND CTS RTS DSR RS232 Pa A Micro DSUB Male Connector Soldered on the Adapter Terminal Cable on the CPU Board SYS68K CPU 40 41 USER S MANUAL FOR...

Page 52: ...e rack The following signals are driven received from the CPU board Signal Driven Received From SYSCLK X FGA 002 Gate Array BR3 X FGA 002 Gate Array BR 3 0 X 4 Level Arbiter BG 3 0 OUT X 4 Level Arbit...

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Page 54: ...on 3 Unplug every other VMEbus board to avoid conflicts 2 1 Power ON Power to the VMEbus rack may be switched on when the board is correctly installed the switches are in the correct positions and the...

Page 55: ...matter of a few seconds until all tests are completed Once all tests are completed the following messages will appear on the screen VMEPROM Hardware Selftest I O test passed Memory test passed Clock t...

Page 56: ...sec 275 LFM 1 4 meter sec CFM Cubic Feet per Minute LFM Linear Feet per Minute The TARGET 32 chassis performs forced air cooling using four axial fans The amount of airflow needed for cooling and norm...

Page 57: ...HARDWARE USER S MANUAL...

Page 58: ...This page was intentionally left blank...

Page 59: ...SRM 01 4 3 9 3 2 11 Summary of the SRM 01 4 3 9 3 2 12 The SRM 01 8 3 10 3 2 13 RAM Type Information for the SRM 01 8 3 11 3 2 14 Summary of the SRM 01 8 3 11 3 3 The System EPROM Area 3 12 3 3 1 Mem...

Page 60: ...iver Modules FH002 and FH003 3 58 3 8 12 Summary of DUSCC2 3 58 3 9 The PI T 68230 3 59 3 9 1 Address Map of the PI T1 Registers 3 60 3 9 2 I O Configuration of PI T1 3 61 3 9 3 Rotary Switches 3 62 3...

Page 61: ...ter 6 12 6 4 3 The VMEbus Release Function 6 18 6 4 3 1 Release Every Cycle REC 6 18 6 4 3 2 Release on Request ROR 6 18 6 4 3 3 Release After Timeout RAT 6 18 6 4 3 4 Release on Bus Clear RBCLR 6 19...

Page 62: ...3 Figure 3 16 Location Diagram of RS232 RS422 RS485 Driver Receivers J20 and J21 plus Resistor Arrays J22 and J23 3 44 Figure 3 17 Connection Between DUSCC2 and D Sub Connector for RS232 3 49 Figure 3...

Page 63: ...nfiguration Jumperfield Setting 3 55 Table 3 13 PCB Locations for RS232 RS422 RS485 Configuration 3 56 Table 3 14 PI T1 Register Layout 3 60 Table 3 15 PI T1 Interface Signals 3 61 Table 3 16 PI T2 Re...

Page 64: ...vi This page was intentionally left blank...

Page 65: ...arallel real time operation and responsiveness The EAGLE modules are installed on the CPU board via the FLXi FORCE Local eXpansion interface This provides a full 32 bit interface between the base boar...

Page 66: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 This page intentionally left blank...

Page 67: ...e hit or miss These signals are used to decode the memory map of the CPU board The transfer start TS signals the hardware on the CPU board that the current cycle is not a cache cycle and that the deco...

Page 68: ...for MC68020 MC68030 not for MC68040 14 038 Format Error 15 03C Uninitialized Interrupt 16 23 040 05C Unassigned Reserved 24 060 Spurious Interrupt 25 064 Level 1 Interrupt Autovector 26 068 Level 2 In...

Page 69: ...microprocessor is connected via jumper B17 to the devices When using the CPU board this jumper must be inserted according to the following figure CAUTION If jumper B17 is removed damage may be caused...

Page 70: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 2 4 Figure 2 2 Location Diagram of Jumperfields B17...

Page 71: ...signals in addition to used address and data signals The FGA 002 Gate Array serves as a manager for the VMEbus All VMEbus address and data lines are connected to the gate array through the buffers Add...

Page 72: ...and written in user mode memory can only be read If an access from the VMEbus takes place the onboard logic requests the local bus mastership from the local arbiter via the FGA 002 Gate Array After th...

Page 73: ...are described in the following chapters which also contain the RAM Type Information description RAM Type Information on PI T2 PI T Bit Name Value Description PB0 MCD0 Describes the memory size of the...

Page 74: ...rammable in 4 Kbyte steps through the FGA 002 The defined memory range can be write protected in coordination with the address modifier codes For example in supervisor mode the memory can be read and...

Page 75: ...3 0 3 2 4 RAM Type Information for the DRM 03 The following information can be read from the PI T2 RAM Type Information PI T Bit Name DRM 03 4 PB0 MCD4 1 PB1 MCD1 1 PB2 MCD2 0 PC2 RAMTYP 1 PC4 BURST...

Page 76: ...access address for the VMEbus is programmable in 4 Kbyte steps through the FGA 002 The defined memory range can be write protected in coordination with the address modifier codes For example in super...

Page 77: ...e Information for the DRM 05 The following information can be read from the PI T2 RAM Type Information PI T Bit Name DRAM 05 16 DRAM 05 32 PB0 MCD4 1 0 PB1 MCD1 0 0 PB2 MCD2 0 0 PC2 RAMTYP 1 1 PC4 BUR...

Page 78: ...ss address for the VMEbus is programmable in 4 Kbyte steps through the FGA 002 The defined memory range can be write protected in coordination with the address modifier codes For example in supervisor...

Page 79: ...I T Bit Name Value PB0 MCD4 1 PB1 MCD1 1 PB2 MCD2 0 PC2 RAMTYP 0 PC4 BURST 1 PC6 PARITY 0 3 2 11 Summary of the SRM 01 4 Capacity 4 Mbytes Address Range 00000000 to 003FFFFF Port Data Width 32 bits Lo...

Page 80: ...VMEbus is programmable in 4 Kbyte steps through the FGA 002 The defined memory range can be write protected in coordination with the address modifier codes For example in supervisor mode the memory c...

Page 81: ...I T Bit Name Value PB0 MCD4 0 PB1 MCD1 1 PB2 MCD2 0 PC2 RAMTYP 0 PC4 BURST 1 PC6 PARITY 0 3 2 14 Summary of the SRM 01 8 Capacity 8 Mbytes Address Range 00000000 to 007FFFFF Port Data Width 32 bits Lo...

Page 82: ...l Program Counter The data path of the System EPROM Area is 32 bits wide The system EPROM consists of two 16 bit wide EPROM devices 3 3 1 Memory Organization of the System EPROM Area The memory organi...

Page 83: ...SECTION 3 HARDWARE USER S MANUAL 3 13 Figure 3 2 Location Diagram of the System EPROM Area...

Page 84: ...low Device Locations Address UU UM XXX0 XXX1 J30 UPPER XXX4 XXX5 XXX8 XXX9 XXXC XXXD LM LL XXX2 XXX3 J29 LOWER XXX6 XXX7 XXXA XXXB XXXE XXXF CAUTION 1 The bus size of the System EPROM Area cannot be c...

Page 85: ...M Area Device Device Capacity Total Capacity Default Configuration 27210 64K x 16 256 Kbytes 272048 128K x 16 512 Kbytes X UNDEFINED 256K x 16 1 Mbyte UNDEFINED 512K x 16 2 Mbytes The default configur...

Page 86: ...3 3 Configuration Jumper Settings of System EPROM Area Jumperfield B11 Jumpersetting Device Organization B11 1 o o o o o o 27C210 64K x 16 B11 1 o o o o o o 27C2048 128K x 16 DEFAULT B11 1 o o o o o o...

Page 87: ...SECTION 3 HARDWARE USER S MANUAL 3 17 Figure 3 4 Location Diagram of Jumperfield B11 Configuration of the System EPROM Area...

Page 88: ...city of the used devices The following table lists the address map of the EPROM area Table 3 1 Address Map of the EPROM Area Start Address End Address Used Device Total Capacity Default Configuration...

Page 89: ...the VMEbus P2 connector The aim of the EAGLE module concept is to be more flexible in the I O part of the board This circumvents the complete redesign of a board if new I O devices or customer specif...

Page 90: ...simulates the dynamic bus sizing so that succeeding bytes seen by the microprocessor are handled in the same manner as succeeding bytes for the FLASH EPROM Byte word and long word accesses are managed...

Page 91: ...ite protection jumper on jumperfield B16 must be set from 1 2 to 2 3 The following page shows the location of jumperfield B16 3 5 3 Address Map of the FLASH EPROM The address range of the FLASH EPROM...

Page 92: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 22 3 5 6 Location Diagram of Jumperfield B16...

Page 93: ...ures a byte port External hardware simulates the dynamic bus sizing so that succeeding bytes seen by the microprocessor are handled in the same manner as succeeding bytes for the Local SRAM Byte word...

Page 94: ...n the CPU board is supplied via the same jumperfield B1 B1 1 o Battery is connected to 1 o Battery is cut from Backup Supply Line Backup Supply Line o default o B20 B20 1 o 5VSTDBY is connected to 1 o...

Page 95: ...SECTION 3 HARDWARE USER S MANUAL 3 25 Figure 3 5 Location Diagram of the Backup Supply Jumperfield B1 and B20...

Page 96: ...unchangeable The SRAM is used by the boot software and therefore not fully available to the user Please refer to the FGA 002 User s Manual Section 10 Boot Software 3 6 3 Summary of the SRAM Area Not...

Page 97: ...e Boot EPROM is 27512 with the total memory capacity of 64 Kbytes The location is J15 For more detailed information over the Boot EPROM please refer to Section 10 Boot Software Description of the FGA...

Page 98: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 28 Figure 3 6 Location Diagram of the Boot EPROM...

Page 99: ...al full duplex synchronous asynchronous receiver and transmitter Multiprotocol operation consisting of BOP HDLC ADCCP SDLC SDLC Loop X 25 or X 75 link level COP BISYNC DDCMP X 21 ASYNC 5 8 bit plus op...

Page 100: ...W DUSRPR Receiver Parameter Reg FF802007 07 R W DUSRTR Receiver Timing Reg FF802008 08 R W DUSCTPRH Counter Timer Preset Reg H FF802009 09 R W DUSCTPRL Counter Timer Preset Reg L FF80200A 0A R W DUSC...

Page 101: ...B 00 R W DUSOMR Output and Miscellaneous Reg FF80202C 0C R DUSCTH Counter Timer High FF80202D 0D R DUSCTL Counter Timer Low FF80202E 0E 00 R W DUSPCR Pin Configuration Reg FF80202F 0F R W DUSCCR Chann...

Page 102: ...are installed in the default configuration The I O signals of port 1 are connected to the VME connector P2 as follows Signal Input Output VME Connector P2 Description DCD X c29 Data Carrier Detect RX...

Page 103: ...s the connection between the DUSCC and the VMEbus Connector P2 and the Micro D Sub connector CAUTION Before installing the 0S resistors to generate the port 1 availability on the VMEbus P2 Connector p...

Page 104: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 34 Figure 3 7 Location Diagram of the 0S S Resistors R563 to R569...

Page 105: ...17 11 10 19 12 14 5 DUSCC 68562 CHANNEL A B Pin No Pin No 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TXD SOU OU2 OU1 RTC TRC CTS IN1 DCD RXD 19 02 14 16 06 17 10 07 18 01 13 15 04 09 08 05 FH002 Ba 12 9 8...

Page 106: ...S MANUAL FORCE COMPUTERS 3 36 The devices are labeled as shown in the following chart Port Channel Ba Bb Pa Connector 1 a B3 B5 PD1 1 VME P2 2 b B4 B6 PD2 2 The next figure shows the pinout of the Mic...

Page 107: ...SECTION 3 HARDWARE USER S MANUAL 3 37 Figure 3 11 Location Diagram of RS232 Configuration Jumperfields B3 B4 B5 and B6...

Page 108: ...from FORCE COMPUTERS 3 8 4 RS422 RS485 Hardware Configuration of Ports 1 and 2 The CPU board is delivered with RS232 compatible interface buffers installed on all serial I O ports It is possible to re...

Page 109: ...The next figure shows the location diagram of the 0S resistors R563 to R569 and the figure afterwards displays the connection between the DUSCC1 and the VMEbus connector CAUTION Before installing the...

Page 110: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 40 Figure 3 12 Location Diagram of the 0S S Resistors R563 to R569...

Page 111: ...8 13 12 W1 W2 W3 W4 W6 W5 W8 W7 A29 TXD A30 RTS A31 CTS A32 RXD C32 RXD C31 CTS C30 RTS C29 TXD 39 45 36 37 43 44 35 48 42 40 15 9 17 11 10 19 12 14 18 5 SECTION 3 HARDWARE USER S MANUAL 3 41 Figure 3...

Page 112: ...ces that have to be inserted according to the RS232 RS422 RS485 configuration Table 3 7 PCB Locations for the RS232 RS422 RS485 Configuration Port RS232 Devices RS422 RS485 Devices Driver and Receiver...

Page 113: ...SECTION 3 HARDWARE USER S MANUAL 3 43 Figure 3 15 Location Diagram of RS422 RS485 Configuration Jumperfields B3 B4 B5 and B6...

Page 114: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 44 Figure 3 16 Location Diagram of RS232 RS422 RS485 Driver Receivers J20 and J21 plus Resistor Arrays J22 and J23...

Page 115: ...OMPUTERS has developed the RS232 and RS422 RS485 modules with the FH002 and FH003 These 21 pin SIL modules are installed with sockets so that they may be easily changed The default jumper setting on t...

Page 116: ...DUSRPR Receiver Parameter Reg FF802207 07 R W DUSRTR Receiver Timing Reg FF802208 08 R W DUSCTPRH Counter Timer Preset Reg H FF802209 09 R W DUSCTPRL Counter Timer Preset Reg L FF80220A 0A R W DUSCTC...

Page 117: ...r Timing Reg FF802228 08 R W DUSCTPRH Counter Timer Preset Reg H FF802229 09 R W DUSCTPRL Counter Timer Preset Reg L FF80222A 0A R W DUSCTCR Counter Timer Control Reg FF80222B 0B 00 R W DUSOMR Output...

Page 118: ...ected to the local 8 bit data bus and is accessible in the byte mode The RS232 interfaces of port 3 and 4 which are wired to the two 9 pin Micro D Sub connectors named 3 and 4 on the front panel are i...

Page 119: ...39 45 36 37 43 44 35 48 42 40 15 9 18 17 11 10 19 12 14 5 SECTION 3 HARDWARE USER S MANUAL 3 49 Figure 3 17 Connection Between DUSCC2 and D Sub Connector for RS232 The devices are labeled as shown in...

Page 120: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 50 Figure 3 18 Location Diagram of RS232 Configuration Jumperfields B7 through B10...

Page 121: ...ed on the Adapter Terminal Cable on the CPU Board SECTION 3 HARDWARE USER S MANUAL 3 51 The following is the displayed pinout of the D Sub connector for RS232 Configuration Figure 3 19 RS232 Pinout of...

Page 122: ...e to reconfigure I O ports 3 and 4 so that they are RS422 RS485 compatible Termination resistors can be installed to adapt various cable lengths and reduce reflections The resistor value is user appli...

Page 123: ...1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ja 5V 15 09 01 05 18 08 13 12 W1 W2 W3 W4 W6 W5 W8 W7 39 45 36 37 43 44 35 48 42 40 15 17 11 10 19 12 9 14 18 5 SECTION 3 HARDWARE USER S MANUAL 3 53 Figu...

Page 124: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 54 Figure 3 21 Location Diagram of RS422 RS485 Configuration Jumperfields B7 through B10...

Page 125: ...tor Soldered on the CPU Board B Micro DSUB and DSUB Female Connectors on the Adapter Terminal Cable SECTION 3 HARDWARE USER S MANUAL 3 55 Figure 3 22 RS422 RS485 Pinout of the Micro D Sub and D Sub Co...

Page 126: ...J25 J25 J27 4 J26 J26 J28 The RS422 RS485 compatible interface supports TXD RXD RTS CTS with differential outputs and inputs Each port occupies the same nine pins of the D Sub connector as in the RS23...

Page 127: ...SECTION 3 HARDWARE USER S MANUAL 3 57 Figure 3 23 Location Diagram of RS232 RS422 RS485 Driver Receiver J25 J26 and Resistor Arrays J27 J28...

Page 128: ...nd FH003 These 21 pin SIL modules are installed with sockets so that they may be easily changed The default jumper setting on the CPU board for the RS232 module is as shown below B7 B8 B9 B10 1 o o 16...

Page 129: ...nal modes either 8 or 16 bits wide The PI T contains a 24 bit wide counter and a 5 bit prescaler Features of the PI T MC68000 Bus Compatible Port Modes Include Bit I O Unidirectional 8 bit and 16 bit...

Page 130: ...egister FF800C04 04 00 PIT1 PCDDR Port C Data Direction Register FF800C05 05 00 PIT1 PIVR Port Interrupt Vector Register FF800C06 06 00 PIT1 PACR Port A Control Register FF800C07 07 00 PIT1 PBCR Port...

Page 131: ...TS Table 3 15 PI T1 Interface Signals PI T1 I O Pin PI T Signal Name Connected Signal Input Output 4 PA0 Rotary Switch 1 I 5 PA1 I 6 PA2 I 7 PA3 I 9 PA4 Rotary Switch 2 I 10 PA5 I 11 PA6 I 12 PA7 I 14...

Page 132: ...I T1 in relation to the rotary switch signals Rotary Switch Signals Assignment PI T1 Signal Rotary Switch Bit Data Bit of PI T Port A PA0 SW1 1 0 0 PA1 SW1 2 1 1 PA2 SW1 3 2 2 PA3 SW1 4 3 3 PA4 SW2 1...

Page 133: ...SECTION 3 HARDWARE USER S MANUAL 3 63 Figure 3 24 CPU Board Front Panel and Rotary Switch Positions...

Page 134: ...e resolved there with considerable time expense To prevent the software from being concerned the following feature is implemented on the CPU 40 41 Rev 2 and succeeding revisions The signal ENARMC 16 c...

Page 135: ...to generate an interrupt because the handshake lines are not used and are reserved 3 9 6 A24 Slave Mode In order to allow an A24 slave mode as described in the chapter Address Modifier Decoding and A2...

Page 136: ...41 USER S MANUAL FORCE COMPUTERS 3 66 3 9 8 Summary of PI T1 Device 68230 PI T Access Address FF800C00 Port Width Byte Interrupt Request Level Software programmable FGA 002 Interrupt Channel Timer IR...

Page 137: ...FF800E04 04 00 PIT2 PCDDR Port C Data Direction Register FF800E05 05 00 PIT2 PIVR Port Interrupt Vector Register FF800E06 06 00 PIT2 PACR Port A Control Register FF800E07 07 00 PIT2 PBCR Port B Contr...

Page 138: ...ction No 5 COPIES OF DATA SHEETS Table 3 18 PI T2 Interface Signals PI T I O Pin PI T Signal Name Connected Signal Input Output 4 PA0 I O 5 PA1 I O 6 PA2 I O 7 PA3 I O 9 PA4 I O 10 PA5 I O Port via I...

Page 139: ...al TOUT PI T2 pin 37 is used as an interrupt request line The 24 bit timer can generate interrupt requests on a software programmable level Together with the Port Interrupt Request line the timer inte...

Page 140: ...onnected to PI T2 port A and are used as inputs or outputs the remaining four bits are connected to the PI T2 handshake pins This port can be used to build a Centronics type interface PI T Header B12...

Page 141: ...SECTION 3 HARDWARE USER S MANUAL 3 71 Figure 3 25 Location Diagram of Header B12...

Page 142: ...Module Configuration Signals PC2 PC4 PC6 From PC2 RAMTYP of the RAM module can be read as shown in the following chart PC2 RAM Type 1 DRAM 0 SRAM For more information please refer to the chapter The S...

Page 143: ...ted in 2 3 With a jumper inserted in 1 2 this bit can generate a RESET which is equivalent to a Powerup RESET so that the contents of a RAM disk in DRAM area can be destroyed 3 9 18 PIRQ PC5 Interrupt...

Page 144: ...not used In order to retain compatibility to following versions this line should not be used in any applications 3 9 21 Summary of PI T2 Device 68230 PI T Access Address FF800E00 Port Width Byte Inte...

Page 145: ...it Register FF803002 02 RTC1MIN 1 Minute Digit Register FF803003 03 RTC10MIN 10 Minute Digit Register FF803004 04 RTC1HR 1 Hour Digit Register FF803005 05 RTC10HR PM AM and 10 Hour Digit Register FF80...

Page 146: ...y _sday unsigned char rtc day10reg 0x03 10 rtc day1reg 0x0f sy _smon unsigned char rtc mon10reg 0x01 10 rtc mon1reg 0x0f rtc dcontrol 0 start clock write RTC 72421 from RAM 30 Oct 87 M S writeclock sy...

Page 147: ...d via this jumperfield B1 B1 1 o Battery is connected to 1 o Battery is cut from Backup Supply Line Backup Supply Line o default o B20 B20 1 o 5VSTDBY is connected to 1 o 5VSTDBY is cut from Backup Su...

Page 148: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 78 Figure 3 27 Location Diagram of the Backup Supply Jumperfield B1 and B20...

Page 149: ...RTC Access Address FF80 3000 Access Mode Byte only Supported Transfers Byte only the upper 4 bits are to be ignored for read and write accesses Battery Type Varta CR 1 3 or equivalent Interrupt Reque...

Page 150: ...the VMEbus For more information please refer to the chapter VMEbus RESET Conditions In combination with the ABORT switch the RESET switch has a special function which is described in the BOOT Softwar...

Page 151: ...s provided through this LED whether or not the board is working on VME 4 5 Rotary Switches There are two rotary switches SW1 and SW2 which are four bit hexadecimal encoded These switches are completel...

Page 152: ...SECTION 3 HARDWARE USER S MANUAL 4 3 Figure 4 1 Front Panel of the CPU Board...

Page 153: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 4 4 This page was intentionally left blank...

Page 154: ...The Gate Array installed on the CPU board handles all local and VMEbus interrupts Each interrupt request from the local bus through the two DUSCCs RTC the two timers as well as the Gate Array specifi...

Page 155: ...02 Device Base Address Function Local Interrupt FGA 002 Pin Request Number Number RTC FF803000 0 C07 PI T1 FF800C00 Timer IRQ 2 E07 PI T2 FF800E00 3 A06 DUSCC1 FF802000 4 B06 DUSCC2 FF802200 5 B05 Mor...

Page 156: ...connected to the FGA 002 which can optionally map every level and then interrupt the local CPU A four level bus arbiter together with several release functions are implemented with all slot 1 function...

Page 157: ...E can be set to 16 or 32 bits The default setup after RESET through the hardware is 32 bits VMEPROM contains a command MEM to set up the data bus transfer size of the software programmable areas MEM d...

Page 158: ...rd x x x x y Unaligned Word x x y Unaligned x x x y Long Word A Unaligned x x x y Long Word B RMW Byte x y RMW Byte x y RMW Word x x y RMW Long Word x x x x y RMW Read Modify Write Table 6 3 Defined V...

Page 159: ...1 A15 A16 All allowed and defined Address Modifier AM Codes are listed in the next table The supported AM codes are marked with an asterisk The address range of the microprocessor 4 Gigabyte is split...

Page 160: ...eserved 37 H H L H H H Reserved 36 H H L H H L Reserved 35 H H L H L H Reserved 34 H H L H L L Reserved 33 H H L L H H Reserved 32 H H L L H L Reserved 31 H H L L L H Reserved 30 H H L L L L Reserved...

Page 161: ...L L L Reserved 17 L H L H H H Reserved 16 L H L H H L Reserved 15 L H L H L H Reserved 14 L H L H L L Reserved 13 L H L L H H Reserved 12 L H L L H L Reserved 11 L H L L L H Reserved 10 L H L L L L R...

Page 162: ...FE FFFF 111001 NDA FBFF 0000 VMEbus Short I O Access 101101 SDA A16 D32 D24 D16 D8 101001 NDA FBFF FFFF FC00 0000 111110 SPA VMEbus Standard Access 111101 SDA A24 D16 D8 111010 NPA FCFE FFFF 111001 ND...

Page 163: ...6 2 3 Address Modifier Decoding and A24 Slave Mode For access to the shared RAM from the VMEbus side extended A32 and standard A24 accesses are allowed The FGA 002 only recognizes A32 accesses The ac...

Page 164: ...cess address for VMEbus is programmed to Start Address 10000000 End Address 10400000 the PI T bits must be programmed to PI T1 Port B Bit 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 to allow A24 accesses If an A2...

Page 165: ...AM Codes HEX Code Address Modifier Function 5 4 3 2 1 0 3E H H H H H L Standard Supervisory Program Access 3D H H H H L H Standard Supervisory Data Access 3A H H H L H L Standard Previleged Program A...

Page 166: ...se an interrupt on a different level to the processor So for example a VMEbus interrupt request on level 2 can be mapped to cause an interrupt request on level 5 to the processor CAUTION The CPU board...

Page 167: ...ependent 6 4 2 The On Board Four Level Arbiter The CPU board contains a four level arbiter which can be enabled disabled through hardware The four level arbiter together with the VMEbus request level...

Page 168: ...Mode Default Label Description HEX HEX Value FF803E02 00 R W 73 ARBRE Arbiter Requester Register G Table 6 9 Description of Arbiter Requester Register Bits Bit Value Mode Description 0 1 R W Request l...

Page 169: ...er Arbiter Jumperfield B19 If the control of the request level is done by software the request level is selected via bit 0 and bit 1 of the register The bit settings for the VMEbus request levels 0 to...

Page 170: ...ee Table 6 9 Description of Requester Arbiter Register Bits Arbiter Mode The arbiter mode of the onboard VMEbus arbiter can be selected by software via bit 2 and bit 3 of the requester arbiter registe...

Page 171: ...Disabled Bus Request Level 3 B19 default B19 1 6 1 6 2 o o 5 2 o o 5 3 4 3 4 o o o o o o o o Bus Request Level 2 B19 B19 1 6 1 6 2 o o 5 2 o o 5 3 4 3 4 o o o o o o o o Bus Request Level 1 B19 B19 1 6...

Page 172: ...SECTION 3 HARDWARE USER S MANUAL 6 17 Figure 6 2 Location Diagram of Jumperfield B19...

Page 173: ...s and data strobes If the REC mode is enabled all other bus release functions have no impact don t care The REC mode is only for CPU cycles to the VMEbus and not for DMA cycles The programming of the...

Page 174: ...ways a CPU or DMA Controller mastership Gaining mastership is always a VMEbus arbitration sequence 6 4 3 6 Release Voluntary RV If the local processor is VMEbus bus master the release on request count...

Page 175: ...6 20 Table 6 12 Bus Release Functions Function Enabled Release REC Yes Every Cycle ROR Y RAT Y RBCLR X REC NO BR 0 1 2 0 ROR Y or RAT Y Timeout RBCLR NO REC NO BR 0 1 2 0 or ROR Y Timeout or BCLR 0 RA...

Page 176: ...They are accessed on addresses FF803E00 and FF803E01 Table 6 13 VMEbus Interrupter Registers Default I O Base Address FF800000 Default Offset 00003E00 Address Offset Mode Default Label Description HE...

Page 177: ...rupt IRQ4 1 Active 0 Inactive automatically set to zero again 5 R W VMEbus interrupt IRQ5 1 Active 0 Inactive automatically set to zero again 6 R W VMEbus interrupt IRQ6 1 Active 0 Inactive automatica...

Page 178: ...SYSCLK signal can be enabled and disabled via a jumper setting at B13 Jumper 1 8 inserted SYSCLK driven default Jumper 1 8 removed SYSCLK not driven The usage of jumperfield B13 is shown in Figure 6 3...

Page 179: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 24 Figure 6 4 Location Diagram of B13...

Page 180: ...lization of external intelligent I O boards The ACFAIL line is ignored by VMEPROM The FGA 002 drives the SYSFAIL line after Reset until initialization of the board is completed To remain compatible to...

Page 181: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 26 Figure 6 6 Location Diagram of Jumperfield B13...

Page 182: ...serted the SYSRESET signal of the VMEbus backplane will be asserted When the RUN LED is red the processor is in the HALT state For example this state will be entered if a double bus fault occurs A res...

Page 183: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 28 Figure 6 8 Location Diagram of Jumperfield B2...

Page 184: ...o 1 2 3 4 6 8 3 2 Drive RESET to VMEbus To drive the RESET signal on the VMEbus jumper B13 3 6 must be inserted on the CPU board When inserted the RESET from the front panel switch and voltage monito...

Page 185: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 30 Figure 6 9 Location Diagram of Jumperfield B13...

Page 186: ...ly supported by the CPU board The RESET instruction triggers the RESET generator and resets all peripherals on the board driving RESET to low At this point the processor on the CPU itself will not be...

Page 187: ...APPENDIX TO THE HARDWARE USER S MANUAL...

Page 188: ...This page was intentionally left blank...

Page 189: ...EPROM SOCKETS D 1 Pin Assignment for EPROM Area E CIRCUIT SCHEMATICS OF CPU BOARD E 1 Circuit Schematics of DRM 01 E 2 Circuit Schematics of SRM 10 F DEFAULT JUMPER SETTINGS ON THE CPU BOARD G CONNEC...

Page 190: ...ii This page was intentionally left blank...

Page 191: ...ets 2 Data Path 32 bits Serial I O Interfaces 68562 4 RS232 RS422 RS485 Compatible 4 of 4 24 bit Timer with 5 bit Prescaler 2 8 bit Timer 1 Parallel I O Interface 68230 12 lines Real Time Clock with O...

Page 192: ...TINUED Power Requirements 5V min min 5 2A 6 0A 12V min max 0 1A 0 3A 12V min max 1 0A 0 3A Operating Temperature with Forced Air Cooling 0 to 50EC Storage Temperature 40 to 85C Relative Humidity nonco...

Page 193: ...y A32 D32 D24 D16 D8 01000000 F9FFFFFF VMEbus Addresses 16 Mbyte Shared Memory A32 D32 D24 D16 D8 FA000000 FAFFFFFF Message Broadcast Area FB000000 FBFEFFFF VMEbus A24 D32 D24 D16 D8 FBFF0000 FBFFFFFF...

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Page 195: ...Reg FF802007 07 R W DUSRTR Receiver Timing Reg FF802008 08 R W DUSCTPRH Counter Timer Preset Reg H FF802009 09 R W DUSCTPRL Counter Timer Preset Reg L FF80200A 0A R W DUSCTCR Counter Timer Control Re...

Page 196: ...0 R W DUSOMR Output and Miscellaneous Reg FF80202C 0C R DUSCTH Counter Timer High FF80202D 0D R DUSCTL Counter Timer Low FF80202E 0E 00 R W DUSPCR Pin Configuration Reg FF80202F 0F R W DUSCCR Channel...

Page 197: ...iver Timing Reg FF802208 08 R W DUSCTPRH Counter Timer Preset Reg H FF802209 09 R W DUSCTPRL Counter Timer Preset Reg L FF80220A 0A R W DUSCTCR Counter Timer Control Reg FF80220B 0B 00 R W DUSOMR Outp...

Page 198: ...80222B 0B 00 R W DUSOMR Output and Miscellaneous Reg FF80222C 0C R DUSCTH Counter Timer High FF80222D 0D R DUSCTL Counter Timer Low FF80222E 0E 00 R W DUSPCR Pin Configuration Reg FF80222F 0F R W DUSC...

Page 199: ...PIVR Port Interrupt Vector Register FF800C06 06 00 PIT1 PACR Port A Control Register FF800C07 07 00 PIT1 PBCR Port B Control Register FF800C08 08 PIT1 PADR Port A Data Register FF800C09 09 PIT1 PBDR...

Page 200: ...rt Interrupt Vector Register FF800E06 06 00 PIT2 PACR Port A Control Register FF800E07 07 00 PIT2 PBCR Port B Control Register FF800E08 08 PIT2 PADR Port A Data Register FF800E09 09 PIT2 PBDR Port B D...

Page 201: ...TC10MIN 10 Minute Digit Register FF803004 04 RTC1HR 1 Hour Digit Register FF803005 05 RTC10HR PM AM and 10 Hour Digit Register FF803006 06 RTC1DAY 1 Day Digit Register FF803007 07 RTC10DAY 10 Day Digi...

Page 202: ...SYS68K CPU 40 41 FORCE COMPUTERS C 8 This page was intentionally left blank...

Page 203: ...19 20 22 21 2 7 2 1 0 2 7 2 1 0 VPP CE D15 D14 D13 D12 VCC PGM NC A15 A14 A13 A12 A11 A10 D11 D10 D9 D8 A9 GND GND D7 D6 D5 D4 D3 D2 D1 A8 A7 A6 A5 A4 A3 A2 D0 OE A1 A0 SECTION 4 APPENDIX TO THE HARDW...

Page 204: ...SYS68K CPU 40 41 FORCE COMPUTERS D 2 This page was intentionally left blank...

Page 205: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 1 APPENDIX E CIRCUIT SCHEMATICS OF CPU BOARD...

Page 206: ...SYS68K CPU 40 41 FORCE COMPUTERS E 2 This page was intentionally left blank...

Page 207: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 3 E 1 Circuit Schematics of DRM 01...

Page 208: ...SYS68K CPU 40 41 FORCE COMPUTERS E 4 This page was intentionally left blank...

Page 209: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 5 E 2 Circuit Schematics of SRM 01...

Page 210: ...SYS68K CPU 40 41 FORCE COMPUTERS E 6 This page was intentionally left blank...

Page 211: ...mper Settings for System EPROMs and SRAM EEPROM Jumperfield Description Default Schematics Connection B11 System EPROM device select 1 6 SH5 A4 B16 FLASH EPROM write dis enable 1 2 SH4 C2 Default Jump...

Page 212: ...s RESET 3 6 Receive VMEbus RESET 4 5 Default Jumper Settings for Test Jumperfield Description Default Schematics Connection B17 Clock Signal to CPU 1 2 SH16 A1 Headers for 12 Bit I O and 8 Bit I O Jum...

Page 213: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL F 3 Location Diagram for All Jumperfields...

Page 214: ...SYS68K CPU 40 41 FORCE COMPUTERS F 4 This page was intentionally left blank...

Page 215: ...D04 BF0OUT D12 6 D05 BG1IN D13 7 D06 BG1OUT D14 8 D07 BG2IN D15 9 GND BG2OUT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BR0 SYSRESET 13 DS0 BR1 LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTAC...

Page 216: ...9 X A29 X 10 X A30 X 11 X A31 X 12 X GND X 13 X 5V X 14 X D16 X 15 X D17 X 16 X D18 X 17 X D19 X 18 X D20 X 19 X D21 X 20 X D22 X 21 X D23 X 22 X GND X 23 X D24 X 24 X D25 X 25 X D26 X 26 X D27 X 27...

Page 217: ...odule that provides or decodes an address on address lines A01 through A31 ADDRESS ONLY CYCLE A DTB cycle that consists of an address broadcast but no data transfer SLAVES do not acknowledge ADDRESS O...

Page 218: ...paths needed for wider data and address transfers Still others have a single PC board that provides the signal conductors and connectors of both the J1 and J2 backplanes BACKPLANE INTERFACE LOGIC Spe...

Page 219: ...r one or two 96 pin connectors that can be plugged into 1014 backplane connectors BUS TIMER A functional module that measures how long each data transfer takes on the DTB and terminates the DTB cycle...

Page 220: ...IDs over D00 D31 DAISY CHAIN A special type of 1014 signal line that is used to propagate a signal level from board to board starting with the first slot and ending with the last slot There are four b...

Page 221: ...cycle initiated by an INTERRUPT HANDLER that reads a STATUS ID from an INTERRUPTER An INTERRUPT HANDLER generates this cycle when it detects an interrupt request from an INTERRUPTER and it has contro...

Page 222: ...tion Since most systems are powered by an AC source the power monitor is typically designed to detect drop out or brown out conditions on AC lines READ CYCLE A DTB cycle used to transfer 1 2 or 4 byte...

Page 223: ...R and when those cycles specify their participation transfers data between itself and the MASTER SLOT A position where a board can be inserted into a 1014 backplane If the 1014 system has both a J1 an...

Page 224: ...ned fashion UTILITY BUS One of the four buses provided by the 1014 backplane This bus includes signals that provide periodic timing and coordinate the power up and power down of 1014 systems WRITE CYC...

Page 225: ...THE HARDWARE USER S MANUAL I 1 APPENDIX I LITERATURE REFERENCE Please refer to the following books for more detailed information 1 MC 68040 Users Manual 2 VMEbus Standards 2618 S Shannon Tempe Arizon...

Page 226: ...SYS68K CPU 40 41 FORCE COMPUTERS I 2 This page was intentionally left blank...

Page 227: ...HAS ACHIEVED A VERY HIGH STANDARD OF QUALITY IN PRODUCTS AND DOCUMENTATION SUGGESTIONS FOR IMPROVEMENT ARE ALWAYS WELCOME ANY FEEDBACK YOU CARE TO OFFER WOULD BE APPRECIATED PLEASE USE ATTACHED PRODUC...

Page 228: ...COPIES OF DATA SHEETS...

Page 229: ...COPIES OF DATA SHEETS RTC 72423 DUSCC 68562 PI T 68230...

Page 230: ...USERS NOTES...

Page 231: ...USERS NOTES...

Page 232: ...USERS NOTES...

Page 233: ...OPTIONS APPLICATIONS MODIFICATIONS...

Page 234: ...INTRODUCTION TO VMEPROM IN USE WITH THE SYS68K CPU 40 41...

Page 235: ...d Interrupt Sources 2 5 2 5 The On Board Real Time Clock 2 5 3 CONCEPT OF VMEPROM 3 1 3 1 Getting Started 3 1 3 2 Command Line Syntax 3 1 3 3 VMEPROM Commands 3 2 4 SPECIAL VMEPROM COMMANDS FOR CPU BO...

Page 236: ...ge 1 6 Table 2 Program After Reset 1 6 Table 3 Boot an Operating System 1 6 Table 4 Examples in Using the Rotary Switches 1 7 Table 5 On board I O Devices 2 2 Table 6 On board Interrupt Sources 2 4 Ta...

Page 237: ...isassembler supporting all 68040 instructions Numerous commands for program debugging including breakpoints tracing processor register display and modify Display and modify floating point data registe...

Page 238: ...quence also reads the Real Time Clock RTC of the CPU board and initializes the software clock of the kernel If a terminal is connected to the terminal port of the CPU board the VMEPROM banner and the...

Page 239: ...e command level of VMEPROM If ABORT is pressed while a user program is under execution all user registers are saved at the current location of the program counter and the message Aborted Task is displ...

Page 240: ...are usable from VMEPROM will be installed If an EAGLE 01C is installed this bit indicates whether the RAM disk should be initialized after reset If this bit is set to 0 the RAM disk is initialized as...

Page 241: ...ult filename is SY STRT If the bit is 1 VMEPROM comes up with the default banner Bit 0 If this switch is set to 0 VMEPROM checks the VMEbus for available hardware after reset In addition VMEPROM waits...

Page 242: ...0 RAM DISK AT 40800000 512 Kbytes Table 2 Program After Reset Bit 3 Bit 2 Lower Switch SW1 1 1 VMEPROM OR USER PROGRAM at same location 1 0 USER PROGRAM AT FFC81000 0 1 Autoboot System 0 0 USER PROGR...

Page 243: ...is on top of memory VMEPROM will be started No start file will be executed The available hardware on the VMEbus will not be checked 4 C RAM Disk initialization will be done if an EAGLE 01C is installe...

Page 244: ...YRAM 00007000 00007FFF Task Control Block 0 00008000 User Memory of Task 0 Mail Array RAM Disk optional Hashing buffer Management Entity ME Please note that the size of the first task cannot be extend...

Page 245: ...to VMEPROM shell 5 K M 3 3 3 5 BIOS Modules 5 5 Kernel 5 5 File Manager 5 K M 5 EPROM resident installable devices and tables 5 K M 3 3 5 VMEPROM Initialization Code 5 K M 3 5 User Alterable Memory Lo...

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Page 247: ...OF THE CPU BOARD 2 1 EPROM RAM Layout Address Device 0000 0000 9 Local RAM FF00 0000 9 EPROM Area FF7F FFFF FFC0 0000 9 SRAM Area FFC7 FFFF FFC8 0000 9 FLASH EPROM Area FFCF FFFF FFE0 0000 9 EPROM Ar...

Page 248: ...of onboard I O devices Table 5 On board I O Devices BASE ADDRESS DEVICE FF803000 RTC 72423 FF802000 DUSCC1 68562 FF802200 DUSCC2 68562 FF800C00 PI T1 68230 FF800E00 PI T2 68230 FFD00000 FGA 002 FF8034...

Page 249: ...the EAGLE Module ID EPROM 000016 00 Device base address FEC01600 The ID EPROM base address of EAGLE Modules is always at FE800000 Additional EPROMs RAM always start at FD800000 Beginning with chip sel...

Page 250: ...levels which are defined by VMEPROM All interrupt levels and vectors of the onboard I O devices are software programmable via the FGA 002 Gate Array Table 6 On board Interrupt Sources DEVICE INTERRUP...

Page 251: ...or are summarized in Table 7 In order for these boards to work correctly with VMEPROM the listed interrupt vectors may not be used Table 7 Off board Interrupt Sources Board Interrupt Level Interrupt V...

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Page 253: ...s Manual for the pinning of the D Sub connector and the required handshake signals 3 Power supply 5V 12V 12V must be present See the Hardware User s Manual for the power consumption of the CPU board...

Page 254: ...of VMEPROM All the common commands of VMEPROM are described in detail in the VMEPROM User s Manual Those commands which are specific for the hardware of the CPU board are described in the following p...

Page 255: ...used to select the Standard Access Mode for the VMEbus Additionally the VMEbus interrupts can be enabled or disabled Example ARB cr Current arbiter mode enabled Mode Prioritized ROUND ROBIN Set arbit...

Page 256: ...marized for all supported boards in the Appendix of this manual Additional memory must be contiguous to the on board memory of the CPU board This memory is cleared by the config command to allow DRAM...

Page 257: ...any value a new one has to be entered in binary form If only a cr is entered no change will be made To step backward a minus has to be entered If a or ESC is given the FGA command returns to the shell...

Page 258: ...able buffered write mode for the local SCSI controller If no argument is entered all modified hashing buffers are flushed If an argument of ON or OFF is given the buffered write mode will be enabled o...

Page 259: ...r the device driver task The device driver task has to flush its buffers periodically every time seconds Please refer to the USER S MANUAL of the EAGLE Module to see fi the device driver taks is able...

Page 260: ...efines a range of slot numbers Slot numbers can range from 0 to 21 A slot number of 0 sends the message to all slots The second parameter defines which FMB channel should be used It can be 0 or 1 The...

Page 261: ...t Data Bus Width of the VMEbus Format MEM MEM 16 MEM 32 This command can display or set the data bus width of the CPU board on the VMEbus If no argument is entered the current data bus width is displa...

Page 262: ...e third parameter length specifies the length of the FLASH EPROM If 0 is entered the length and width is automatically calculated The fourth parameter width selects the data width of the FLASH EPROMs...

Page 263: ...ill be reported This test also checks if reading from and writing to the floppy disk controller and the SCSI controller proceeds as expected 3 2 Memory test on the memory of the current task The follo...

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Page 265: ...K PDOS Force Disk Format Utility 07 Sep 88 Possible Disk Controllers in this System are Controller 1 is not defined Controller 2 is not defined Controller 3 is a Force ISCSI 1 Controller 4 is a onboar...

Page 266: ...ns 6 of Floppy Partitions 15 First track for PDOS Parts 0 Last track for PDOS Parts 10219 First PDOS disk 2 Total of Logical Tracks 10220 Disk Logical Trks Physical Trks PDOS sectors Base Top Base Top...

Page 267: ...it Command Q Exit to Select Drive Update Param RAM Y N Y System Parameter RAM Updated Select Menu W W0 W15 Winch F F0 F8 Floppy Q Quit Select Drive Q After formatting the disk all logical partitions m...

Page 268: ...APPENDIX TO THE INTRODUCTION TO VMEPROM...

Page 269: ...Table of VMEPROM E 1 F Benchmark Source Code F 1 G Special Locations G 1 H Generation of Applications in EPROM H 1 H1 General Information H 1 H1 1 Replacing the User Interface H 1 I Introduction to t...

Page 270: ...DISK DRIVER FORCE EAGLE ME ADDR FF004E30 DISK DRIVER FORCE EAGLE 01C ADDR FF007FF0 UART DRIVER FORCE CPU 40 41 DUSCC ADDR FF004500 UART DRIVER FORCE SIO 1 2 ADDR FF004800 UART DRIVER FORCE ISIO 1 2 AD...

Page 271: ...the INSTALL command The following must be entered INSTALL U2 FF004800 In order to install one of the ports of the SIO boards in VMEPROM the BP command can be used The SIO 1 2 boards use the driver ty...

Page 272: ...00 In order to install one of the ports of an ISIO board in VMEPROM the BP command can be used The ISIO 1 2 boards are driver type 3 In order to install the first port of an ISIO board with a 9600 bau...

Page 273: ...stalled automatically The VMEPROM FRMT command must be used for defining the following factors The physical structure of the drive i e number of heads number of cylinders drive select number etc The b...

Page 274: ...2 of the floppy interface selects high or normal density When this signal is low level it 3 designates normal density mode VMEPROM only operates under normal density Pin 4 should be the Eject signal...

Page 275: ...ble Slot Base Address 1 80000000 2 84000000 3 88000000 4 8C000000 21 D0000000 A6 1 UART Driver A6 1 1 Onboard EAGLE Module To install the UART driver type INSTALL U7 FF008610 The UART driver can handl...

Page 276: ...15 ports To select a specific port use the BP command The BP command expects a UART base address This address is a logical address 1 for the first physical serial device 2 for the second and so on The...

Page 277: ...05 1 8 5 Now port 5 is connected to the second serial device on the EAGLE module The baud rate is set to 9600 baud The handshake is set to XON XOFF A6 2 Disk Driver VMEPROM supports up to two floppy d...

Page 278: ...S3 records transmitted in a particular block The count appears in the address field There is no code data field Not supported by VMEPROM S7 A termination record for a block of S3 records The address...

Page 279: ...8044CB1 S214020010203C0000020E428110C1538066FA487AE4 S214020020001021DF0008487A001221DF000C4E750E S21402003021FC425553200030600821FC41444452C2 XX Check sum XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Data 0200XX...

Page 280: ...ge size define MBZ MMZ MPZ memory bitmap size define NMB MBZ 8 number of map bytes define FSS 38 file slot size define TQB 2 TCB index define TQM TQB 4 map index define TQE TQM 2 event 1 event 2 defin...

Page 281: ...file expand count 0FB char _pidn processor ident byte 0FC long _begn abs addr of K1 BEGN table 100 int _rwcl 14 port row col 1 15 11C char _opip 15 output port pointers 1 15 158 char _uart 16 uart ba...

Page 282: ...s are stored in the following order define VBR 0 define SFC 1 define DFC 2 define CACR 4 define PC 5 define SR 6 define USTACK 7 define SSTACK 8 define MSTACK 9 define D0 10 10 17 D0 D7 define A0 18 1...

Page 283: ...err XERR address 44A char _cmd command line delimiter 44B BYTE _tid task id 44C char _ecf echo flag 44D char _cnt output column counter 44E char _mmf memory modified flag 44F char _prt input port 450...

Page 284: ...ing GO T etc 7FC char VMEMSP 202 Master stack handle w care 8C6 char VMESSP 802 supervisor stack handle w care BE8 char VMEPUSP 802 vmeprom internal user stack F0A LWORD f_fpreg 3 8 floating point dat...

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Page 286: ...038 Format Error 15 03C Uninitialized Interrupt 16 040 THROUGH Unassigned Reserved 23 05C 24 060 Spurious Interrupt 25 064 AV1 26 068 AV2 27 06C AV3 28 070 AV4 29 074 AV5 30 078 AV6 31 07C AV7 32 080...

Page 287: ...Used from the IBC UART driver 198 318 Mailbox 6 Used from the EAGLE disk driver 199 31C Mailbox 7 Used from the IBC disk driver 200 320 THROUGH Reserved 223 37C 224 380 Timer 225 384 Reserved 226 388...

Page 288: ...D xdef BEN8BEG BEN8END xdef BEN9BEG BEN9END xdef BEN10BEG BEN10END xdef BEN11BEG BEN11END xdef BEN12BEG BEN12END xdef BEN13BEG BEN13END xdef BEN14BEG BEN14END page benchmark execution benchex address...

Page 289: ...BNE S 090 MOVE L A0 A2 MOVE L A1 A3 MOVE W D0 D4 BMI S 030 020 CMP B A2 A3 DBNE D4 020 BNE S 012 030 SUB W D1 D2 032 MOVEM L A7 D3 D4 A2 A3 RTS 090 MOVEQ L 1 D2 BRA S 032 END EDN BENCH 1 EDN1DAT DC B...

Page 290: ...123 D1 BSR S EDN2 SUBQ L 1 D4 BNE S 010 RTS EDN2 SUB W 2 D0 BEQ S 020 SUBQ W 1 D0 BEQ S 030 010 BFTST A0 D1 1 DC W E8D0 DC W 0841 SNE D2 RTS 020 BFSET A0 D1 1 DC W EED0 DC W 0841 SNE D2 RTS 030 BFTST...

Page 291: ...0001 DC B 01110010 DC B 10000000 EVEN PAGE BENCH 6 CACHE TEST 128KB PROGRAM IS EXECUTED 1000 TIMES CAUTION THIS BENCHMARK NEEDS 128 KBYTE MEMORY LEA L 010 PC A2 MOVE L 203A0000 D1 OPCODE FOR MOVE L 0...

Page 292: ...1 010 FMUL X FP0 FP1 SUBQ L 1 D5 BNE S 010 RTS page PDOS BENCHMARK 1 CONTEXT SWITCHES MOVE L 100000 D6 000 XSWP CONTEXT SWITCH SUBQ L 1 D6 DONE BGT S 000 N RTS PAGE PDOS BENCHMARK 2 EVENT SET MOVEQ L...

Page 293: ...AGE CLR L D0 SELECT TASK 0 LEA L MES01 PC A1 POINT TO MESSAGE MOVE L 100000 D6 000 XSTM SEND MESSAGE XKTM READ MESSAGE BACK SUBQ L 1 D6 DONE BGT S 000 N RTS MES01 DC B BENCH 13 0 EVEN PAGE PDOS BENCHM...

Page 294: ...am location and RAM disk addresses These options can be selected by front panel switches The locations shown in the table can be changed by the user to adapt VMEPROM to every environment To make the n...

Page 295: ...need this ident to make sure that below data is valid 54 DS B 1 03 Bit 0 If this bit is 0 no message occurs indicating that VMEPROM is waiting until the hard disk is up to speed This bit is only consi...

Page 296: ...500 bytes No registers are predefined If the reserved supervisor stack space is not sufficient the stack pointer has to be set to point to an appropriate address in RAM H1 1 Replacing the User Interf...

Page 297: ...oduction to VMEPROM Both the user and the supervisor stack are located in the task control block The user stack has a reserved space of 800 bytes and the supervisor stack a space of 800 bytes The prog...

Page 298: ...ask through the RAM port as well 1 I 1 Accessing the RAM port through the ACI Before any data can be exchanged through the RAM port an application has to gain the ownership of the RAM port in the same...

Page 299: ...ed long response_mode unsigned long data_exchange_mode unsigned long application_address unsigned long _remnant 47 Figure 1 Structure of the CCB used to gain RAM port ownership The OPEN Command is to...

Page 300: ...long _remnant 48 Figure 2 Structure of CCB used to read data from RAM port The READ command is described in the Application Command Interface Programming Guide Special paramters are count The Managem...

Page 301: ...ng _remnant 48 Figure 3 Structure of CCB used to write data to RAM port The WRITE command is described in the Application Command Programming Guide Special parameters are count The Management Entity a...

Page 302: ...he appropriate routine of the VMEPROM kernel dealing with the character input to interprete received control characters or to pass the control characters through the kernel without any processing If t...

Page 303: ...USER S MANUAL FORCE COMPUTERS I 6 H reserved for the VMEPROM kernel s internal purpose F reserved for the VMEPROM kernel s internal purpose 7 6 5 4 3 2 1 0 F H P I 8 D C S Figure 4 RAM Port UART Driv...

Page 304: ...re 10 Application Management Entity s RAM port driver VMEPROM Command RAM port Interface UART driver K2 CHRI 0 127 WRITE 2 Receive Buffer UDxG RDptr RxDptr 0 127 READ Transmit Buffer UDxP TxDptr WRptr...

Page 305: ...to the kernel of VMEPROM via a specific call The RPINTR flag is modified upon the state of the I flag in the RAM port s port flag whenever the routine UxDB of the VMEPROM s RAM port UART driver is ca...

Page 306: ...directly into the applications VMEPROMs memory Positive return values indicate a successful OPEN READ VMEPROM always tries to read exactly 1 character The read mode is set to 00000002 The WAIT bit is...

Page 307: ...ervice code is used from VMEPROM It is service number 1026 It has to set the UART parameter The following service parameters have to be supported service parameter 0 to define the baudrate used VALUE...

Page 308: ...BITS 0 1 1 2 service_parameter 3 to define the parity to be used VALUE PARITY 0 no 1 even 2 odd service_parameter 4 to define the flow control to be used VALUE FLOW CONTROL 0 no handshake 1 XON XOFF 2...

Page 309: ...hat VMEPROM works properly with the device driver task OPEN VMEPROM executes the OPEN command with a data exchange mode of C0000000 Therefore the device driver task has to support Direct Memory Access...

Page 310: ...he parameters used are _remnant 0 the drive number 0 or 1 _remnant 1 reserved any value should be ignored The following return values are allowed VALUE DESCRIPTION 0 Read successfully completed 32 Rec...

Page 311: ...The parameters used are _remnant 0 the drive number 0 or 1 _remnant 1 reserved any value should be ignored The following return values are allowed VALUE DESCRIPTION 0 Write successfully completed 32 R...

Page 312: ...e following services have to be supported from the device driver task SERVICE CODE DESCRIPTION 2049 Set Floppy Parameter 2050 Format Floppy The possible return values are listed in the READ WRITE comm...

Page 313: ...tep rate 1 Parameters for the format floppy service service parameter 0 drive number 0 or 1 service parameter 1 address of an interleave table The interleave table must have as many entries as the flo...

Page 314: ...ess Furthermore it has to have the possibility to transfer the data directly into the applications VMEPROMs memory The parameters used are _remnant 0 Buffer count If the device driver task is able to...

Page 315: ...until the data is read The parameters used are _remnant 0 SCSI bus ID as returned from the get device list service _remnant 1 Logical block size VMEPROM uses a block size of 256 bytes The following re...

Page 316: ...e _remnant 0 SCSI bus ID as returned from the get device list service _remnant 1 Logical block size VMEPROM uses a block size of 256 bytes The following return values are allowed VALUE DESCRIPTION 0 R...

Page 317: ...Device List service input parameter service_parameter 0 address of a buffer for the returned data service_parameter 1 maximum length of the buffer returned data status Structure of the returned data...

Page 318: ...the get device list service service_parameter 1 SCSI command byte 0 3 service_parameter 2 SCSI command byte 4 7 service_parameter 3 SCSI command byte 8 11 service_parameter 4 pointer to data buffer se...

Page 319: ...THE APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE...

Page 320: ...This page was intentionally left blank...

Page 321: ...4 1 4 3 Error Codes Related To The CLOSE Command 4 2 4 4 Error Code Related To The READ Command 4 2 4 5 Error Code Especially Related To The WRITE Command 4 2 4 6 Error Codes Related To The SERVICE Co...

Page 322: ...SERVICE command to gain generic information about the devices accessible through the Application Command Interface This command is also used to modify device parameters to get use of special services...

Page 323: ...ilable devices or other information about the EAGLE modules or to issue the OPEN command to establish a logical connection between the application and a specific device However before the application...

Page 324: ...on to indicate that the Command Control Buffer is passed tothe Application Command Interface in order to be processed and cleared by the Application Command Interface to signal that the Command Contro...

Page 325: ...ations NON_SHARABLE devices and only one application can establish a logical connection to such a device The device classes can be distinguished by the minor device number assigned to the correspondin...

Page 326: ...ed command are passed through this area to the application The generic structure of a Command Control Buffer is described below usingthe C programming language elements typedef struct _ccb unsigned lo...

Page 327: ...en carried out and the Command Control Buffer is returned to the application Thus the application may get use of the BUSY semaphore to detect the completion of a command The FINAL semaphore marks the...

Page 328: ...ntry long last_command This entry contains the command code of the last command issued through the Application Command Interface The application should not affect this entry unsigned long _remnant 7 T...

Page 329: ...mand is issued through the Application Command Interface the underlying software verifies whether it is necessary to initialize the specific physical device If a physical device can be owned by more t...

Page 330: ...CAL DEVICE NUMBER inquiry_mode The inquiry mode describes the way the application prefers to gain the attention of the Application Command Interface when it will issue subsequent commands Virtually th...

Page 331: ...tion of a command and may identify one of the following four modes The POLLING mode where the application has to verify the state of the BUSY semaphore within the Access Control Field of the certain C...

Page 332: ...umber Minor Interrupt Number Interrupt Source 1 0 VMEbus interrupt 1 1 VMEbus interrupt 2 2 VMEbus interrupt 3 3 VMEbus interrupt 4 4 VMEbus interrupt 5 5 VMEbus interrupt 6 6 VMEbus interrupt 7 2 0 F...

Page 333: ...bers In contrast to the inquiry mode it is possible to specify the POLL mode in this case the application has to detect the completion of a command upon the state of the BUSY semaphore within the Acce...

Page 334: ...nterrupt Number Interrupt Source 0 0 No interrupt POLL mode 1 0 VMEbus interrupt 1 1 VMEbus interrupt 2 2 VMEbus interrupt 3 3 VMEbus interrupt 4 4 VMEbus interrupt 5 5 VMEbus interrupt 6 6 VMEbus int...

Page 335: ...application If the GLOBAL flag is cleared then the application assumes that the device driver provides a buffer used to accumulate the data received from a physical device or to store the data to be t...

Page 336: ...em_call CCB ccb_link long last_command unsigned long _reserved 7 long status CCB ccb long ccb_number unsigned long ACI_inquiry_address unsigned long _remnant 49 CCB_OPEN_STATUS _access_control_flags T...

Page 337: ...hin the response mode are not consistent For example if the MAILBOX mode is specified but one or more of the most significant 16 bits are set ACI_E_OPEN_ILLEGAL_DATA_EXCHANGE_MODE An illegal data exch...

Page 338: ...mand Interface by either a mailbox interrupt or a FMB interrupt then it contains according to the major and minor interrupt number of the inquiry mode the address of the particular mailbox or FMB chan...

Page 339: ...nd Interface The particular Command Control Buffer is structured as described below typedef struct _ccb_close_command unsigned long _access_control_flags long ME_system_call CCB ccb_link long last_com...

Page 340: ...the completion of the command All other semaphore are unaffected status The status reports the course of the command and indicates one of the following cases ACI_OK Indicates the successful terminati...

Page 341: ...long ME_system_call CCB ccb_link long last_command unsigned long _reserved 7 long command unsigned char buffer unsigned long count unsigned long block_number unsigned long read_mode unsigned long _rem...

Page 342: ...urther information please refer to the detailed description of the device driver The WAIT flag controls whether the READ command has to be carried out either in the wait or the status mode If this fla...

Page 343: ...nsigned long _reserved 7 long status unsigned char buffer unsigned long count unsigned long block_number unsigned long read_mode unsigned long _remnant 48 CCB_READ_STATUS _access_control_flags The BUS...

Page 344: ...device driver and still addresses the beginning of the buffer where the data read from the device have been stored count Contains the number of data blocks and bytes read from the device In case of a...

Page 345: ...ags long ME_system_call CCB ccb_link long last_command unsigned long _reserved 7 long command unsigned char buffer unsigned long count unsigned long block_number unsigned long write_mode unsigned long...

Page 346: ...d description of the device driver The WAIT flag controls whether the WRITE command has to be carried out either in the wait or the status mode If this flag is set the wait mode is selected In this ca...

Page 347: ...ommand unsigned long _reserved 7 long status unsigned char buffer unsigned long count unsigned long block_number unsigned long write_mode unsigned long _remnant 48 CCB_WRITE_STATUS _access_control_fla...

Page 348: ...vice driver and still addresses the beginning of the buffer containing the data which have been written to the device count Contains the number of data blocks and bytes written to the device In case o...

Page 349: ...functions implemented in the peripheral like timers counters etc or to change the operating mode of the device driver The structure of the Command Control Buffer to issue a SERVICE command is describe...

Page 350: ...iver Please refer to the appropriate EAGLE Module s Firmware User s Manual to get detailed information about the services provided by the device drivers dealing with the devices on the particular EAGL...

Page 351: ...ore are both cleared to signal the completion of the command All other semaphores are unaffected status The status reports the state of the completion of the command and either indicates the successfu...

Page 352: ...cular device driver service_parameter Depending on the required service further information is returned to the application through this area of the Command Control Buffer The number of parameters and...

Page 353: ...e of this value represents the major device number in this case 2 which corresponds to a device on an available EAGLE module that is of the same type as specified by a parameter of the SERVICE command...

Page 354: ...ntrol Buffer associated with the logical connection The entry ccb_link within the first part of each Command Control Buffer addresses the following Command Control Buffer and the NULL pointer identifi...

Page 355: ...pecific number of Command Control Buffers 3 The application must have prepared all Command Control Buffers in the chain according to the rules mentioned above before the chain is passed through the Ap...

Page 356: ...s_control_flags long ME_system_call CCB ccb_link long last_command unsigned long _reserved 7 long command long ccb_number unsigned long reserved 50 CCB_ALLOCATE_COMMAND _access_control_flags The BUSY...

Page 357: ...CB chain_head unsigned long reserved 51 CCB_ALLOCATE_STATUS _access_control_flags The BUSY and the PROCESS flags are both cleared to signal the completion of the command All other flags are unaffected...

Page 358: ...he particular Command Control Buffer is structured as described below typedef struct _ccb_free_command unsigned long _access_control_flags long ME_system_call CCB ccb_link long last_command unsigned l...

Page 359: ...s_control_flags long ME_system_call CCB ccb_link long last_command unsigned long _reserved 7 long status unsigned long reserved 52 CCB_FREE_STATUS _access_control_flags The BUSY and the PROCESS flags...

Page 360: ...re described in the appropriate Firmware User s Manual of the EAGLE module 4 1 Common Error Codes ACI_OK 0 ACI_E_ILLEGAL_COMMAND 1 ACI_E_INCONSISTENT_COMMAND_CHAIN 2 ACI_E_BUS_ERROR 3 4 2 Error Codes...

Page 361: ...LOSE_CANNOT_DEACTIVATE_DEVICE_DRIVE 6 R 4 4 Error Code Related To The READ Command ACI_E_READ_NO_CONNECTION 5 4 5 Error Code Especially Related To The WRITE Command ACI_E_WRITE_NO_CONNECTION 5 4 6 Err...

Page 362: ...TERFACE PROGRAMMING GUIDE 4 3 4 7 Error Codes Especially Related To The CCB_ALLOCATE Command ACI_E_ALLOCATE_ILLEGAL_NUMBER_OF_CCBS 4 ACI_E_ALLOCATE_INSUFFICIENT_CCBS 5 4 8 Error Codes Especially Relat...

Page 363: ...TE 0x08L define CLOSE 0x0CL define SERVICE 0x10L define ALLOCATE 31 define BUSY 30 define GET_LOGICAL_DEVICE_NUMBER 1L define POLL 0x00 define MBOX0 0x30 define IRQL2 0x200L struct _ccb_t unsigned lon...

Page 364: ...t _ccb_sclose_status unsigned long _access_control_flags long _ME_system_call struct _ccb_t ccb_link long last_command unsigned long _reserved 7 long status unsigned long _remnant 52 struct _ccb_read_...

Page 365: ...ber unsigned long write_mode unsigned long _remnant 48 struct _ccb_cservice_command unsigned long _access_control_flags long _ME_system_call struct _ccb_t ccb_link unsigned long last_command unsigned...

Page 366: ...ng 0x04L 0x00ffffff get address of CCB0 get_ccb ccb_ptr get the first CCB if found check_device ccb_ptr 2L 0L 0 check for a floppy controller if open_device ccb_ptr found 0 there is one try to open it...

Page 367: ...ss in ccb_address CCB address out Nothing description do_mbox0 initiates a Mailbox 0 interrupt If the CCB is onboard the interrupt will come to myself If the CCB is offboard the interrupt will be gene...

Page 368: ...service_number ccb_ptr command SERVICE we do a SERVICE call ccb_ptr service service_number set requested service number ccb_ptr _access_control_flags 1L BUSY we have to set the BUSY bit do_mbox0 ccb_p...

Page 369: ...end of check_device call open_device ccb_ptr major_minor in ccb_ptr address of CCB which is to use major_minor Major Minor number of the device out ME return value in the CCB description open_device t...

Page 370: ...r 2 32 set sectors cylinder ccb_ptr parameter 3 1 set bytes sector coded ccb_ptr parameter 4 2 set number of heads ccb_ptr parameter 5 0x20 set R W gap ccb_ptr parameter 6 0x36 set format gap ccb_ptr...

Page 371: ...lock number buffer address where the data is to store drive drive number out STATUS as return from the ME in the CCB description do_me_write writes exactly one block to the given drive It waits until...

Page 372: ...outines do_mbox0 wait_not_busy static long close_device ccb_ptr register struct _ccb_close_command ccb_ptr unsigned long error ccb_ptr command CLOSE we do a CLOSE call ccb_ptr _access_control_flags 1L...

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