Force Computers SYS68K/CPU-40, User Manual

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SECTION 4 APPENDIX TO THE HARDWARE USER'S MANUAL
C-1
APPENDIX C
ADDRESS ASSIGNMENT AND REGISTER LAYOUT OF THE I/O DEVICES
Serial I/O Port #1 (DUSCC1) Register Layout
Port Base Address: $FF802000
Address Offset Reset
HEX HEX Value
Mode Label Description
$FF802000 00 00 R/W DUSCMR1 Channel Mode Reg 1
$FF802001 01 00 R/W DUSCMR2 Channel Mode Reg 2
$FF802002 02 -- R/W DUSSS1R SYN1/Secondary Adr Reg 1
$FF802003 03 -- R/W DUSS2R SYN2/Secondary Adr Reg 2
$FF802004 04 00 R/W DUSTPR Transmitter Parameter Reg
$FF802005 05 -- R/W DUSTTR Transmitter Timing Reg
$FF802006 06 00 R/W DUSRPR Receiver Parameter Reg
$FF802007 07 -- R/W DUSRTR Receiver Timing Reg
$FF802008 08 -- R/W DUSCTPRH Counter/Timer Preset Reg H
$FF802009 09 -- R/W DUSCTPRL Counter/Timer Preset Reg L
$FF80200A 0A -- R/W DUSCTCR Counter/Timer Control Reg
$FF80200B 0B 00 R/W DUSOMR Output and Miscellaneous Reg
$FF80200C 0C -- R DUSCTH Counter/Timer High
$FF80200D 0D -- R DUSCTL Counter/Timer Low
$FF80200E 0E 00 R/W DUSPCR Pin Configuration Reg
$FF80200F 0F -- R/W DUSCCR Channel Command Reg
$FF802010 10
$FF802011 11
$FF802012 12 -- W DUSTFIFO Transmitter FIFO
$FF802013 13
$FF802014 14
$FF802015 15
$FF802016 16 -- R DUSRFIFO Receiver FIFO
$FF802017 17
$FF802018 18 00 R/W DUSRSR Receiver Status Reg
$FF802019 19 00 R/W DUSTRSR Transmitter/Receiver Stat Reg
$FF80201A 1A -- R/W DUSICTSR Input + Counter/Timer Stat Reg
$FF80201C 1C 00 R/W DUSIER Interrupt Enable Reg