Force Computers SYS68K/CPU-40, User Manual

Page: 90 / 372

SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS
3-20
3.5 The Local FLASH EPROM
The CPU board holds a 128K x 8 FLASH EPROM which allows data storage without the need of a battery
or supply via the +5VSTDBY VMEbus line.
3.5.1 Memory Organization of the FLASH EPROM
The FLASH EPROM is connected with the data lines D24 to D31. This device features a byte port. The
cycle control chip (CCC) between the 68040 processor and the FGA-002 simulates the dynamic bus sizing,
so that succeeding bytes seen by the microprocessor are handled in the same manner as succeeding bytes
for the FLASH EPROM. Byte, word, and long word accesses are managed by the dynamic bus sizing of
the microprocessor. For further details, please refer to the CCC description.
Data can be read from any address; odd, even or unaligned in byte, word, or long word format, and written
to any address in byte format.
Example for Data Transfers:
The following instruction is fully supported from the FLASH EPROM Area:
MOVE.X ($FFC8 000Y), D0
X = B = Byte 1 Byte
X = W = Word 2 Bytes
X = L = Long Word 4 Bytes
Y = 0
Y = 1
Y = 2
Y = 3
.
.
.