Force Computers SYS68K/CPU-40, User Manual

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS
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3.8.7 Address Map of the DUSCC2 Registers
The following tables contain the complete register map of DUSCC2.
Table 3-8: Serial I/O Port #3 (DUSCC2) Register Address Map
Port Base Address : $FF802200
Address Offset Reset Mode Label Description
HEX HEX Value
$FF802200 00 00 R/W DUSCMR1 Channel Mode Reg 1
$FF802201 01 00 R/W DUSCMR2 Channel Mode Reg 2
$FF802202 02 -- R/W DUSSS1R SYN1/Secondary Adr Reg 1
$FF802203 03 -- R/W DUSS2R SYN2/Secondary Adr Reg 2
$FF802204 04 00 R/W DUSTPR Transmitter Parameter Reg
$FF802205 05 -- R/W DUSTTR Transmitter Timing Reg
$FF802206 06 00 R/W DUSRPR Receiver Parameter Reg
$FF802207 07 -- R/W DUSRTR Receiver Timing Reg
$FF802208 08 -- R/W DUSCTPRH Counter/Timer Preset Reg H
$FF802209 09 -- R/W DUSCTPRL Counter/Timer Preset Reg L
$FF80220A 0A -- R/W DUSCTCR Counter/Timer Control Reg
$FF80220B 0B 00 R/W DUSOMR Output and Miscellaneous Reg
$FF80220C 0C -- R DUSCTH Counter/Timer High
$FF80220D 0D -- R DUSCTL Counter/Timer Low
$FF80220E 0E 00 R/W DUSPCR Pin Configuration Reg
$FF80220F 0F -- R/W DUSCCR Channel Command Reg
$FF802210 10
,
$FF802211 11
*
$FF802212 12
*
-- W DUSTFIFO Transmitter FIFO
$FF802213 13
-
$FF802214 14
,
$FF802215 15
*
$FF802216 16
*
$FF802217 17
-
-- R DUSRFIFO Receiver FIFO
$FF802218 18 00 R/W DUSRSR Receiver Status Reg
$FF802219 19 00 R/W DUSTRSR Transmitter/Receiver Stat Reg
$FF80221A 1A -- R/W DUSICTSR Input + Counter/Timer Stat Reg
$FF80221C 1C 00 R/W DUSIER Interrupt Enable Reg