Force Computers SYS68K/CPU-40, User Manual

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SECTION 8 APPENDIX TO THE INTRODUCTION TO VMEPROM
I-7
I.3 The Internal Structure of the RAM Port
The RAM port provided by the Management Entity consists of an internal 32 bits width semaphore
register and two 128 byte width circular buffers -
the 'receive' and 'transmit' buffer - each equipped with
two pointers to manage insertion and removal of data. Both, the RAM port driver of the Management
Entity and the RAM port UART driver provided by VMEPROM have access to the internal flag register,
the 'receive' buffer and the 'transmit' buffer of the RAM port as depicted in
Figure 10.
Application Management Entity's RAM port driver VMEPROM
Command RAM port
Interface UART driver
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Figure 5: Internal Structure of the RAM port
Within the context of the RAM port the receive describes the process of writing data through the Application
Command Interface to the RAM port's receive buffer; and the transmit relates to the process of reading data
through the ACI from the RAM port's transmit buffer.
Every access to the RAM port through the ACI and the RAM port's operating mode are controlled by the
specific flags in the internal semaphore register. As shown in
Figure 11 the most significant two bits in this
register are in use and described below: