Force Computers SYS68K/CPU-40, User Manual

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SECTION 3 HARDWARE USER'S MANUAL
3-67
3.9.9 Address Map of the PI/T2 Registers
The PI/T2 is accessible via the 8 bit local I/O bus (byte mode). The following table shows the register layout
of PI/T2.
Table 3-16: PI/T2 Register Layout
Default I/O Base Address: $FF80 0000
Default Offset: $0000 0E00
Default Name: PI_T2
Address Offset Reset
HEX HEX Value
Label Description
FF800E00 00 00 PIT2 PGCR Port General Control Register
FF800E01 01 00 PIT2 PSRR Port Service Request Register
FF800E02 02 00 PIT2 PADDR Port A Data Direction Register
FF800E03 03 00 PIT2 PBDDR Port B Data Direction Register
FF800E04 04 00 PIT2 PCDDR Port C Data Direction Register
FF800E05 05 00 PIT2 PIVR Port Interrupt Vector Register
FF800E06 06 00 PIT2 PACR Port A Control Register
FF800E07 07 00 PIT2 PBCR Port B Control Register
FF800E08 08 -- PIT2 PADR Port A Data Register
FF800E09 09 -- PIT2 PBDR Port B Data Register
FF800E0A 0A -- PIT2 PAAR Port A Alternate Register
FF800E0B 0B -- PIT2 PBAR Port B Alternate Register
FF800E0C 0C -- PIT2 PCDR Port C Data Register
FF800E0D 0D -- PIT2 PSR Port Status Register
FF800E10 10 00 PIT2 TCR Timer Control Register
FF800E11 11 0F PIT2 TIVR Timer Interrupt Vector Register
FF800E12 12 -- PIT2 CPR Counter Preload Register
FF800E13 13 -- " "
FF800E14 14 -- " "
FF800E15 15 -- " "
FF800E16 16 -- PIT2 CNTR Count Register
FF800E17 17 -- " "
FF800E18 18 -- " "
FF800E19 19 -- " "
FF800E1A 1A 00 PIT2 TSR Timer Status Register