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SECTION 4
APPENDIX TO THE HARDWARE USER'S MANUAL
H-7
REQUESTOR
A functional module that resides on the same board as a MASTER or INTERRUPT
HANDLER and requests use of the DTB whenever its MASTER or INTERRUPT HANDLER
needs it.
SERIAL CLOCK DRIVER
A functional module that provides a periodic timing signal that synchronizes operation of
the VMSbus. (Although the 1014 specification defines a SERIAL CLOCK DRIVER for use
with the VMSbus, and although it reserves two backplane signal lines for use by that bus,
the VMSbus protocol is completely independent of the 1014.)
SLAVE
A functional module that detects DTB cycles initiated by a MASTER and, when those
cycles specify their participation, transfers data between itself and the MASTER.
SLOT
A position where a board can be inserted into a 1014 backplane. If the 1014 system has
both a J1 and a J2 backplane (or a combination J1/J2 backplane) each slot provides a pair
of 96-pin connectors. If the system has only a J1 backplane, then each slot provides a
single 96-pin connector.
SUBRACK
A rigid framework that provides mechanical support for boards inserted into the
backplane, ensuring that the connectors mate properly and that adjacent boards do not
contact each other. It also guides the cooling airflow through the system, and ensures
that inserted boards do not disengage themselves from the backplane due to vibration or
shock.
SYSTEM CLOCK DRIVER
A functional module that provides a 16 MHz timing signal on the UTILITY BUS.
Summary of Contents for SYS68K/CPU-40
Page 2: ...INTRODUCTION...
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Page 8: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 1 2 Figure 1 1 Photo of the CPU Board...
Page 9: ...SECTION 1 INTRODUCTION 1 3 Figure 1 2 Block Diagram of the CPU Board...
Page 34: ...SECTION 1 INTRODUCTION 2 21 Figure 2 2 The Front Panel of the CPU Board...
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Page 42: ...INSTALLATION...
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Page 57: ...HARDWARE USER S MANUAL...
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Page 83: ...SECTION 3 HARDWARE USER S MANUAL 3 13 Figure 3 2 Location Diagram of the System EPROM Area...
Page 92: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 3 22 3 5 6 Location Diagram of Jumperfield B16...
Page 141: ...SECTION 3 HARDWARE USER S MANUAL 3 71 Figure 3 25 Location Diagram of Header B12...
Page 152: ...SECTION 3 HARDWARE USER S MANUAL 4 3 Figure 4 1 Front Panel of the CPU Board...
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Page 172: ...SECTION 3 HARDWARE USER S MANUAL 6 17 Figure 6 2 Location Diagram of Jumperfield B19...
Page 179: ...SYS68K CPU 40 41 USER S MANUAL FORCE COMPUTERS 6 24 Figure 6 4 Location Diagram of B13...
Page 187: ...APPENDIX TO THE HARDWARE USER S MANUAL...
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Page 207: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 3 E 1 Circuit Schematics of DRM 01...
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Page 209: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL E 5 E 2 Circuit Schematics of SRM 01...
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Page 213: ...SECTION 4 APPENDIX TO THE HARDWARE USER S MANUAL F 3 Location Diagram for All Jumperfields...
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Page 228: ...COPIES OF DATA SHEETS...
Page 229: ...COPIES OF DATA SHEETS RTC 72423 DUSCC 68562 PI T 68230...
Page 230: ...USERS NOTES...
Page 231: ...USERS NOTES...
Page 232: ...USERS NOTES...
Page 233: ...OPTIONS APPLICATIONS MODIFICATIONS...
Page 234: ...INTRODUCTION TO VMEPROM IN USE WITH THE SYS68K CPU 40 41...
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Page 268: ...APPENDIX TO THE INTRODUCTION TO VMEPROM...
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Page 319: ...THE APPLICATION COMMAND INTERFACE PROGRAMMING GUIDE...