Epson S1C17001, Technical Manual

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12 8-BIT TIMER (T8F)
132 EPSON
S1C17001 TECHNICAL MANUAL
12.8 Fine Mode
Fine mode provides a function that minimizes transfer rate errors.
The 8-bit timer can output a programmable clock signal for use as the UART serial transfer clock. The timer output
clock can be set to the required frequency by selecting the appropriate prescaler output clock and reload data. Note
that errors may occur, depending on the transfer rate. Fine mode extends the output clock cycle by delaying the un-
derflow pulse from the counter. This delay can be specified with the TFMD[3:0] bit (D[11:8]/T8F_CTL register).
∗
TFMD[3:0] : Fine Mode Setup Bits in the 8-bit Timer Control (T8F_CTL) Register (D[11:8]/0x4206)
The TFMD[3:0] bit specifies the delay pattern to be inserted into the 16 underflow intervals. Inserting one delay
extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the same way.
Table 12.8.1: Delay patterns specified by TFMD[3:0]
TFMD[3:0]
Underflow number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0x0 – – – – – – – – – – – – – – – –
0x1 – – – – – – – – – – – – – – – D
0x2 – – – – – – – D – – – – – – – D
0x3 – – – – – – – D – – – D – – – D
0x4 – – – D – – – D – – – D – – – D
0x5 – – – D – – – D – – – D – D – D
0x6 – – – D – D – D – – – D – D – D
0x7 – – – D – D – D – D – D – D – D
0x8 – D – D – D – D – D – D – D – D
0x9 – D – D – D – D – D – D – D D D
0xa – D – D – D D D – D – D – D D D
0xb – D – D – D D D – D D D – D D D
0xc – D D D – D D D – D D D – D D D
0xd – D D D – D D D – D D D D D D D
0xe – D D D D D D D – D D D D D D D
0xf – D D D D D D D D D D D D D D D
D: Indicates the insertion of a delay cycle.
Count clock
Underflow signal (no correction)
Underflow signal (with correction)
Output clock (no correction)
Output clock (with correction)
Delay
15 16
15 16
1
1
Figure 12.8.1: Delay cycle insertion in Fine mode
After the initial resetting, TFMD[3:0] is set to 0x0, preventing insertion of delay cycles.