Programmable Logic Device:
Clock and Sync Registers
Pm8560 User’s Manual
10006609-03
8-12
I2CSDA:
I
2
C Data line
0 Drive a 0 onto the I2C SDA line
1 Drive a 1 onto the I2C SDA line
I2CSCL:
I
2
C Clock line
0 Drive a 0 onto the I2C SCL line
1 Drive a 1 onto the I2C SCL line
CT Bus Status
The CTSR connects or isolates the CT NETREF, C8A, C8B, and connector P13 SIO connec-
tions.
Register 8-14:
CT Bus Status (CTSR), 0x38
reserved:
Default is 000000
PTEN:
Signal PTENB* on connector P13, pin 39 (read only)
0 PTENB inactive
1 PTENB active (default on reset)
CTEN:
CT bus connection (read/write)
0 CT bus isolated
1 CT bus connected
CLOCK AND SYNC REGISTERS
Fig. 8-2
is a detailed diagram of the clock and sync registers 0x40 through 0x5c. This dia-
gram is a tool designed to help configure the TDM interfaces. Refer to the specific CPLD
register for more detail.
7
6
5
4
3
2
1
0
reserved
PTEN
CTEN
Summary of Contents for Pm8560
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Page 36: ...Setup Troubleshooting Pm8560 User s Manual 10006609 03 2 12 ...
Page 54: ...Serial I O Baud Rate Selection Pm8560 User s Manual 10006609 03 5 4 ...
Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...
Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
Page 144: ...Index continued Pm8560 User s Manual 10006609 03 i 4 ...