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PCI Bus Interface:
PMC Connector Pin Assignments
10006609-03
Pm8560
User’s Manual
7-9
IRDY*:
INITIATOR READY tri-state signal indicates that the bus master is ready to complete the
data phase of the transaction.
M66EN:
66 MHz ENABLE, when pulled low, configures the PLL for operation between 25 and 33
MHz. When pulled high, the PLL is configured for operation from 33 MHz to a maximum of
66 MHz.
MONARCH:
MONARCH selects PMC PCI bus enumeration and interrupt controllers after reset. This sig-
nal determines if the module is configured as a monarch or non-monarch.
PAR:
PARITY is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is required
by all PCI agents. This tri-state signal is stable and valid one clock after the address phase,
and one clock after the bus master indicates that it is ready to complete the data phase
(either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains valid until one clock
after the completion of the current data phase.
PERR*:
PARITY ERROR reports parity errors during all PCI transactions (tri-state).
REQ*:
BUS REQUEST indicates to the arbiter that a particular master wants to use the bus (out-
put).
RST*:
RESET assertion brings PCI registers, sequencers, and signals to a consistent state (input).
SERR*:
SYSTEMS ERROR, an open-drain signal, indicates address parity errors.
STOP*:
STOP is a sustained tri-state signal used by the current target to request that the bus master
stop the current transaction.
TDI:
TEST DATA INPUT (JTAG) is used in conjunction with TCK to shift data and instructions into
the Test Access Port (TAP) in a serial bit stream.
TDO:
TEST DATA OUTPUT (JTAG) is used in conjunction with TCK to shift data and instructions
into the Test Access Port (TAP) in a serial bit stream.
TMS:
TEST MODE SELECT (JTAG) controls the state of the TAP controller (input signal).
TRDY*:
TARGET READY is a sustained tri-state signal that indicates the target’s ability to complete
the current data phase of the transaction.
TRST*:
TEST RESET (JTAG) is the asynchronous reset for the JTAG controller (input sighal).
Summary of Contents for Pm8560
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Page 36: ...Setup Troubleshooting Pm8560 User s Manual 10006609 03 2 12 ...
Page 54: ...Serial I O Baud Rate Selection Pm8560 User s Manual 10006609 03 5 4 ...
Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...
Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
Page 144: ...Index continued Pm8560 User s Manual 10006609 03 i 4 ...