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Central Processing Unit:
Microprocessor Core (e500)
10006609-03
Pm8560
User’s Manual
3-3
MICROPROCESSOR CORE (E500)
L1 Cache
The MPC8560 processor implements two separate 32-kilobyte, level-one (L1) instruction
and data caches that are eight-way, set-associative. The L1 supports a four-state modi-
fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ
pseudo-least recently used (PLRU) replacement algorithms within each way.
L2 Cache
The internal 512 kilobyte L2 cache is an eight-way set associative instruction and data
cache. The L2 cache is fully pipelined to provide 32 bytes per clock to the L1 caches. The L2
Control (L2CTL) register configures and operates the L2 SRAM array. The L2CTL is read/write
and contents are cleared during power-on reset.
Interrupts and Exception Processing
The interrupt process begins when an exception occurs. The MPC8560 e500 core processes
three types of interrupts: machine check, critical, or noncritical. Each interrupt type has sep-
arate control and status register sets as listed in the following priority:
Machine Check (highest priority):
Machine Check Save and Restore registers (MCSRR0/MCSRR1) save state when they are
taken, and use rfmci instruction to restore state. The machine check enable bit, MSR[ME],
can mask these interrupts.
Noncritical:
The processor is able to change program flow to handle conditions generated by external
signals, errors, or unusual conditions. The Save and Restore registers, SRR0/SRR1, save state
when they are taken and use the rfi instruction to restore state. The external interrupt
enable bit, MSR[EE], can mask these asynchronous interrupts.
Critical:
The Critical Save and Restore registers, CSRR0/CSRR1, save state when they are taken dur-
ing a noncritical interrupt or regular program flow and use the rfci instruction to restore
state. The critical enable bit, MSR[CE], can mask these interrupts. This interrupt also
includes watchdog timer time-out inputs.
Machine State Register
The Machine State register (MSR) configures the state of the MPC8560. On initial power-up
of the Pm8560, most of the MSR bits are cleared. Refer to the
MPC8560
PowerQuicc III Inte-
grated Communications Processor Reference Manual
for more detailed descriptions of the
individual bit fields.
Summary of Contents for Pm8560
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Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
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