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Programmable Logic Device:
Clock and Sync Registers
10006609-03
Pm8560
User’s Manual
8-17
Primary Clock Source
Whenever the SS_PRIREF frequency changes, enable the Reset Command (register 8-9) bit
MTSSR(4).
Register 8-19:
Primary Clock Source (PCSR), 0x50
RSEL2-RSEL0:
RCLK Select 2-0
000 TDM1 selected
001 TDM2 selected
010 TDM3 selected
011 TDM4 selected
100 TDM5 selected
101 TDM6 selected
110 TDM7 selected
111 TDM8 selected
RCLK:
RCLK
0 Disable
1 Enable
FR1.5:
Framer 1.544 MHz clock
0 Disable
1 Enable
FR2.0:
Framer 2.048 MHz clock
0 Disable
1 Enable
CTC8A:
CT bus C8A 2.048 MHz clock
0 Disable
1 Enable
CTC8B:
CT bus C8B 2.048 MHz clock
0 Disable
1 Enable
7
6
5
4
3
2
1
0
RSEL2
RSEL1
RSEL0
RCLK
FR1.5
FR2.0
CTC8A
CTC8B
Summary of Contents for Pm8560
Page 8: ...Contents continued Pm8560 User s Manual 10006609 03 vi ...
Page 10: ...Pm8560 User s Manual 10006609 03 viii blank page ...
Page 12: ...Pm8560 User s Manual 10006609 03 x blank page ...
Page 14: ...Pm8560 User s Manual 10006609 03 ii blank page ...
Page 36: ...Setup Troubleshooting Pm8560 User s Manual 10006609 03 2 12 ...
Page 54: ...Serial I O Baud Rate Selection Pm8560 User s Manual 10006609 03 5 4 ...
Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...
Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
Page 144: ...Index continued Pm8560 User s Manual 10006609 03 i 4 ...