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PCI Bus Interface:
PMC Connector Pin Assignments
Pm8560 User’s Manual
10006609-03
7-8
PCI Bus Control Signals
The following signals for the PCI interface are available on connectors P11, P12, and P13.
Refer to the PCI specification for detailed usage of these signals. All signals are bi-direc-
tional unless stated otherwise.
Note:
A sustained tri-state line is driven high for one clock cycle before float.
AD00-AD31:
ADDRESS and DATA bus (bits 0-31) tri-state lines are used for both address and data han-
dling. A bus transaction consists of an address phase followed by one or more data phases.
C/BE0*-C/BE3*:
BUS COMMAND and BYTE ENABLES tri-state lines have different functions depending on
the phase of a transaction. During the address phase of a transaction, these lines define the
bus command. During a data phase, the lines are used as byte enables.
CLK:
CLOCK input signal operates between 25 and 66 MHz. The PCI bus clock must be between
25-33 MHz or 50-66 MHz. Operation is not guaranteed outside of these ranges.
DEVSEL*:
DEVICE SELECT tri-state signal indicates when a device on the bus has been selected as the
target of the current transaction.
EREADY:
ENUMERATION READY indicates a non-monarch PMC is ready to respond to PCI bus enu-
meration. See the PCI EREADY bit in “PCI Status (PSR), 0x2C”.
FRAME*:
CYCLE FRAME tri-state line is driven by the current master to indicate the beginning of an
access, and continues to be asserted until transaction reaches its final data phase.
GNT*:
GRANT tri-state input or output signal indicates that access to the bus has been granted to
a particular master. Each master has its own GNT*.
IDSEL:
INITIALIZATION DEVICE SELECT input signal acts as a chip select during configuration read
and write transactions.
INTA*-INTD*:
INITIALIZATION DEVICE SELECT input signal acts as a chip select during configuration read
and write transactions.
53
AD6
3.3 V
no connect
54
AD5
no connect
no connect
55
AD4
no connect
no connect
56
GND
GND
GND
57
V(I/O)
no connect
V(I/O)
58
AD3
EREADY
no connect
59
AD2
GND
no connect
60
AD1
RESET_OUT*
CT_D3
61
AD0
no connect
no connect
62
5 V
3.3 V
GND
63
GND
GND
GND
64
REQ64*
1
MONARCH
no connect
1. 64REQ* is isolated to assure 32-bit mode initiation.
Pin:
P11 Signal:
P12 Signal:
P13 Signal:
Pin:
P11
Signal:
P12 Signal:
P13 Signal:
Summary of Contents for Pm8560
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Page 36: ...Setup Troubleshooting Pm8560 User s Manual 10006609 03 2 12 ...
Page 54: ...Serial I O Baud Rate Selection Pm8560 User s Manual 10006609 03 5 4 ...
Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...
Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
Page 144: ...Index continued Pm8560 User s Manual 10006609 03 i 4 ...