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PCI Bus Interface:
PCI Configuration Registers
Pm8560 User’s Manual
10006609-03
7-4
Accessing The Serial EEPROM VPD
The MPC8560 processor maps all internal registers into the first 1 MB of incoming PCI
memory space, starting at address 8000,0000
16
. Any PCI device can access any internal
MPC8560 register through this window. The I
2
C controller registers are contained within
the MPC8560 internal registers. Write to and read from the I
2
C controller registers to
access the on-board VPD NVRAM device. Reference the
MPC8560
PowerQuicc III Integrated
Communications Processor Reference Manual
for more information on the I
2
C controller
interface.
PCI CONFIGURATION REGISTERS
The
PCI Local Bus Specification
defines the configuration registers within the PCI configura-
tion header (0x00 through 0x3F). The following register map lists the common PCI configu-
ration header as implemented by the MPC8560.
Register 7-2:
MPC8560 PCI Configuration Space Header
Address Offset
(hex)
31 16 15
0
00
Device ID
Vendor ID
04
PCI Bus Status
PCI Bus Command
08
Bus Base Class Code
Subclass Code
Bus Programming
Interface
Revision ID
0C
Built-In Self Test (BIST)
Control
Header Type
Bus Latency Timer
Bus Cache Line Size
10
PCI Configuration and Status Register Base Address register (PCSRBAR)
14
32-Bit Memory Base Address register
18
64-Bit Low Memory Base Address register
1C
64-Bit High Memory Base Address register
20
64-Bit Low Memory Base Address register
24
64-Bit High Memory Base Address register
28
reserved
Summary of Contents for Pm8560
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Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...
Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
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