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Programmable Logic Device:
PLD Register Summary
10006609-03
Pm8560
User’s Manual
8-7
FPPB:
Front Panel Reset (POR_RST)
Set to 1 when the front panel switch caused a reset.
Reset Command
The write-only Reset Command register forces one of several types of resets, as shown
below. A reset sequence is first initiated by writing a one to a single valid bit, then the PLD
performs that particular reset, and the bit is automatically cleared.
Register 8-9:
Reset Command (RCR), 0x24
CPUHR:
CPU Hard Reset
A CPU hard reset also causes resets to the framer, MT9045, flash, GbE. and PMC reset out
(when PROE bit 6 is set).
0 No reset (default)
1 Reset
FRMR:
Framer Reset
0 No reset (default)
1 Reset
MTSSR:
MT9045 System Synchronizer Reset
0 No reset (default)
1 Reset
PMCRO:
PMC Reset Out
This bit allows software to reset the Pm8560 based on the values set in PROE bits [5:0].
0 No reset (default)
1 Reset
I2CR:
I
2
C Reset
This will reset both I
2
C ports.
0 No reset (default)
1 Reset
FLR:
Flash Reset
0 No reset (default)
1 Resets on-board flash to a known state
7
6
5
4
3
2
1
0
CPUHR
reserved
FRMR
MTSSR
PMCRO
I2CR
FLR
GBR
Summary of Contents for Pm8560
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Page 36: ...Setup Troubleshooting Pm8560 User s Manual 10006609 03 2 12 ...
Page 54: ...Serial I O Baud Rate Selection Pm8560 User s Manual 10006609 03 5 4 ...
Page 62: ...TDM Interface Rear Panel I O Connector P14 Pm8560 User s Manual 10006609 03 6 8 ...
Page 72: ...PCI Bus Interface PMC Connector Pin Assignments Pm8560 User s Manual 10006609 03 7 10 ...
Page 112: ...Development Mezzanine Card Troubleshooting Pm8560 User s Manual 10006609 03 10 12 ...
Page 138: ...Monitor Download Formats Pm8560 User s Manual 10006609 03 11 26 ...
Page 144: ...Index continued Pm8560 User s Manual 10006609 03 i 4 ...