Covidien Force FX, Service Manual

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Control Board
4-8
Force FX Electrosurgical Generator C Service Manual
Feedback Microcontroller Memory
The Feedback Controller section uses a Xilinx Spartan XC6SLX9 FPGA (U36) along with a
4 Mbit SST39LF040 NOR Flash memory (U43). However, unlike the Main Controller
section, the Feedback section uses the Block Memory in the FPGA.
The NOR Flash memory acts as a code memory for the Feedback Controller, which does
not have ROM memory. The Flash memory is interfaced to the controller through FPGA
U36.
Shared RAM
The 4K x 8 external shared static RAM is provided by an IDT 71342LA device (U50)
DPRAM with semaphore flags. The shared RAM allows the main microcontroller (U5) and
the feedback microcontroller (U11) to share common variables. It functions as a
communications interface between the main and feedback microcontrollers. It also
provides additional general purpose RAM to these microcontrollers.
I/0 Expansion
The FPGAs used in the Main and Feedback sections provide I/Os logic blocks and to
implement the glue Logic. The FPGA is interfaced to the controller P80C562 on the
parallel address and data bus.
The JTAG port is provided for programming the PROM (Configuration memory of FPGA)
in the Main and Feedback sections. Both the PROMs (U23 and U45) and FPGAs (U16-E
and U36-F) are connected in the JTAG chain.
Keyboard Interface and Activation Inputs
The keyboard interface is a row and column matrix between three-bank selected output
lines (BANK0, BANK1, and BANK2-labeled 413_PA6) of the Dual Supply Bus Transceiver
with Configurable Voltage Translation SN74LVC16T245 (U31). The voltage translator
(U31) signals interface with the FPGA XC65LX9-3CSG225C (U16-D), which is used by the
Main Microcontroller and eight Keyboard input lines (KBD_D0-KBD_D7).
The two Bus Transceiver SN74LVC2T45 (U32-U33) devices receive activation inputs
from the IsoBloc
TM decoding circuits on the Power Supply/RF Board. These two devices
interface with the FPGA (U16-D).