AT90S/LS2333 and AT90S/LS4433
56
ADC Control and Status Register - ADCSR
•
Bit 7 - ADEN: ADC Enable
Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while
a conversion is in progress, will terminate this conversion.
•
Bit 6 - ADSC: ADC Start Conversion
In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Run Mode, a logical ‘1’
must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been
enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated con-
version. This dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the conversion is complete, but before the result is written
to the ADC Data Registers. This allows a new conversion to be initiated before the current conversion is complete. The new
conversion will then start immediately after the current conversion completes. When a dummy conversion precedes a real
conversion, ADSC will stay high until the real conversion completes.
Writing a 0 to this bit has no effect.
•
Bit 5 - ADFR: ADC Free Run Select
When this bit is set (one) the ADC operates in Free Run Mode. In this mode, the ADC samples and updates the data regis-
ters continuously. Clearing this bit (zero) will terminate Free Run Mode.
•
Bit 4 - ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Com-
plete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if
doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
•
Bit 3 - ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
•
Bits 2..0 - ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
Bit
7
6
5
4
3
2
1
0
$06 ($26)
ADEN
ADSC
ADFR
ADIF
ADIE
ADPS2
ADPS1
ADPS0
ADCSR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Table 22. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
