AT90S/LS2333 and AT90S/LS4433
66
Port D Data Register - PORTD
Port D Data Direction Register - DDRD
Port D Input Pins Address - PIND
The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each
Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the
pins are read.
Port D As General Digital I/O
PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is con-
figured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured
as an input pin the MOS pull up resistor is activated. To switch the pull up resistor off the PDn has to be cleared (zero) or
the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes active, even if the
clock is not running.
Table 26. Port D Pins Alternate Functions
Port Pin
Alternate Function
PD0
RXD (UART Input line)
PD1
TXD (UART Output line)
PD2
INT0 (External interrupt 0 input)
PD3
INT1 (External interrupt 1 input)
PD4
T0 (Timer/Counter 0 external counter input)
PD5
T1 (Timer/Counter 1 external counter input)
PD6
AIN0 (Analog comparator positive input)
PD7
AIN1 (Analog comparator negative input)
Bit
7
6
5
4
3
2
1
0
$12 ($32)
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
PORTD
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$11 ($31)
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
DDRD
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$10 ($30)
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
PIND
Read/Write
R
R
R
R
R
R
R
R
Initial value
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
