AT90S/LS2333 and AT90S/LS4433
50
UART Baud Rate Register - UBRR
This is a 12-bit register which contains the UART Baud Rate according to the equation on the previous page. The UBRRHI
contains the 4 most significant bits, and the UBRR contains the 8 least significant bits of the UART Baud Rate.
Analog Comparator
The analog comparator compares the input values on the positive input PD6 (AIN0) and negative input PD7 (AIN1). When
the voltage on the positive input PD6 (AIN0) is higher than the voltage on the negative input PD7 (AIN1), the Analog Com-
parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function.
In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-
rupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 43
.
Figure 43. Analog Comparator Block Diagram
Analog Comparator Control And Status Register - ACSR
•
Bit 7 - ACD: Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the
analog comparator. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE
bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
Bit
15
14
13
12
11
10
9
8
$03 ($23)
-
-
-
-
MSB
LSB
UBRRHI
$09 ($29)
MSB
LSB
UBRR
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$08 ($28)
ACD
AINBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
